1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "px30-robot-no-gpu.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip rk3326 evb lpddr3 v10 board for robot linux"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3326-evb-lp3-v10-robot-linux", "rockchip,rk3326"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun adc-keys { 17*4882a593Smuzhiyun compatible = "adc-keys"; 18*4882a593Smuzhiyun io-channels = <&saradc 2>; 19*4882a593Smuzhiyun io-channel-names = "buttons"; 20*4882a593Smuzhiyun poll-interval = <100>; 21*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun esc-key { 24*4882a593Smuzhiyun linux,code = <KEY_ESC>; 25*4882a593Smuzhiyun label = "esc"; 26*4882a593Smuzhiyun press-threshold-microvolt = <1310000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun home-key { 30*4882a593Smuzhiyun linux,code = <KEY_HOME>; 31*4882a593Smuzhiyun label = "home"; 32*4882a593Smuzhiyun press-threshold-microvolt = <624000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun menu-key { 36*4882a593Smuzhiyun linux,code = <KEY_MENU>; 37*4882a593Smuzhiyun label = "menu"; 38*4882a593Smuzhiyun press-threshold-microvolt = <987000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun vol-down-key { 42*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 43*4882a593Smuzhiyun label = "volume down"; 44*4882a593Smuzhiyun press-threshold-microvolt = <300000>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vol-up-key { 48*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 49*4882a593Smuzhiyun label = "volume up"; 50*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun rk817-sound { 55*4882a593Smuzhiyun compatible = "simple-audio-card"; 56*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 57*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk817-codec"; 58*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 59*4882a593Smuzhiyun simple-audio-card,cpu { 60*4882a593Smuzhiyun sound-dai = <&i2s1_2ch>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun simple-audio-card,codec { 63*4882a593Smuzhiyun sound-dai = <&rk817_codec>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 68*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 69*4882a593Smuzhiyun /*clocks = <&rk817 1>;*/ 70*4882a593Smuzhiyun /*clock-names = "ext_clock";*/ 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * On the module itself this is one of these (depending 76*4882a593Smuzhiyun * on the actual card populated): 77*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 78*4882a593Smuzhiyun * - PDN (power down when low) 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun vccsys: vccsys { 84*4882a593Smuzhiyun compatible = "regulator-fixed"; 85*4882a593Smuzhiyun regulator-name = "vcc3v8_sys"; 86*4882a593Smuzhiyun regulator-always-on; 87*4882a593Smuzhiyun regulator-boot-on; 88*4882a593Smuzhiyun regulator-min-microvolt = <3800000>; 89*4882a593Smuzhiyun regulator-max-microvolt = <3800000>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun wireless-wlan { 93*4882a593Smuzhiyun compatible = "wlan-platdata"; 94*4882a593Smuzhiyun wifi_chip_type = "AP6210"; 95*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&bus_apll { 101*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&cif_new { 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun port { 109*4882a593Smuzhiyun cif_in: endpoint { 110*4882a593Smuzhiyun remote-endpoint = <&gc2155_out>; 111*4882a593Smuzhiyun vsync-active = <0>; 112*4882a593Smuzhiyun hsync-active = <1>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&cpu0 { 118*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&dfi { 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&dmc { 126*4882a593Smuzhiyun center-supply = <&vdd_logic>; 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&emmc { 131*4882a593Smuzhiyun bus-width = <8>; 132*4882a593Smuzhiyun cap-mmc-highspeed; 133*4882a593Smuzhiyun mmc-hs200-1_8v; 134*4882a593Smuzhiyun no-sdio; 135*4882a593Smuzhiyun no-sd; 136*4882a593Smuzhiyun disable-wp; 137*4882a593Smuzhiyun non-removable; 138*4882a593Smuzhiyun num-slots = <1>; 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&i2c0 { 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun clock-frequency = <400000>; 145*4882a593Smuzhiyun i2c-scl-rising-time-ns = <280>; 146*4882a593Smuzhiyun i2c-scl-falling-time-ns = <16>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun rk817: pmic@20 { 149*4882a593Smuzhiyun compatible = "rockchip,rk817"; 150*4882a593Smuzhiyun reg = <0x20>; 151*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 152*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 153*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 154*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 155*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 156*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 157*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 158*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 159*4882a593Smuzhiyun rockchip,system-power-controller; 160*4882a593Smuzhiyun wakeup-source; 161*4882a593Smuzhiyun #clock-cells = <1>; 162*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 163*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 164*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 165*4882a593Smuzhiyun pmic-reset-func = <1>; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun vcc1-supply = <&vccsys>; 168*4882a593Smuzhiyun vcc2-supply = <&vccsys>; 169*4882a593Smuzhiyun vcc3-supply = <&vccsys>; 170*4882a593Smuzhiyun vcc4-supply = <&vccsys>; 171*4882a593Smuzhiyun vcc5-supply = <&vccsys>; 172*4882a593Smuzhiyun vcc6-supply = <&vccsys>; 173*4882a593Smuzhiyun vcc7-supply = <&vcc_3v0>; 174*4882a593Smuzhiyun vcc8-supply = <&vccsys>; 175*4882a593Smuzhiyun vcc9-supply = <&dcdc_boost>; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun pwrkey { 178*4882a593Smuzhiyun status = "okay"; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 182*4882a593Smuzhiyun gpio-controller; 183*4882a593Smuzhiyun #gpio-cells = <2>; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun rk817_ts_gpio1: rk817_ts_gpio1 { 186*4882a593Smuzhiyun pins = "gpio_ts"; 187*4882a593Smuzhiyun function = "pin_fun1"; 188*4882a593Smuzhiyun /* output-low; */ 189*4882a593Smuzhiyun /* input-enable; */ 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun rk817_gt_gpio2: rk817_gt_gpio2 { 193*4882a593Smuzhiyun pins = "gpio_gt"; 194*4882a593Smuzhiyun function = "pin_fun1"; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun rk817_pin_ts: rk817_pin_ts { 198*4882a593Smuzhiyun pins = "gpio_ts"; 199*4882a593Smuzhiyun function = "pin_fun0"; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun rk817_pin_gt: rk817_pin_gt { 203*4882a593Smuzhiyun pins = "gpio_gt"; 204*4882a593Smuzhiyun function = "pin_fun0"; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 208*4882a593Smuzhiyun pins = "gpio_slp"; 209*4882a593Smuzhiyun function = "pin_fun0"; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 213*4882a593Smuzhiyun pins = "gpio_slp"; 214*4882a593Smuzhiyun function = "pin_fun1"; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 218*4882a593Smuzhiyun pins = "gpio_slp"; 219*4882a593Smuzhiyun function = "pin_fun2"; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 223*4882a593Smuzhiyun pins = "gpio_slp"; 224*4882a593Smuzhiyun function = "pin_fun3"; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun regulators { 229*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 230*4882a593Smuzhiyun regulator-always-on; 231*4882a593Smuzhiyun regulator-boot-on; 232*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 233*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 234*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 235*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 236*4882a593Smuzhiyun regulator-name = "vdd_logic"; 237*4882a593Smuzhiyun regulator-state-mem { 238*4882a593Smuzhiyun regulator-on-in-suspend; 239*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 244*4882a593Smuzhiyun regulator-always-on; 245*4882a593Smuzhiyun regulator-boot-on; 246*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 247*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 248*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 249*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 250*4882a593Smuzhiyun regulator-name = "vdd_arm"; 251*4882a593Smuzhiyun regulator-state-mem { 252*4882a593Smuzhiyun regulator-off-in-suspend; 253*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 258*4882a593Smuzhiyun regulator-always-on; 259*4882a593Smuzhiyun regulator-boot-on; 260*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 261*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 262*4882a593Smuzhiyun regulator-state-mem { 263*4882a593Smuzhiyun regulator-on-in-suspend; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun vcc_3v0: DCDC_REG4 { 268*4882a593Smuzhiyun regulator-always-on; 269*4882a593Smuzhiyun regulator-boot-on; 270*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 271*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 272*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 273*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 274*4882a593Smuzhiyun regulator-state-mem { 275*4882a593Smuzhiyun regulator-off-in-suspend; 276*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun vcc_1v0: LDO_REG1 { 281*4882a593Smuzhiyun regulator-always-on; 282*4882a593Smuzhiyun regulator-boot-on; 283*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 284*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 285*4882a593Smuzhiyun regulator-name = "vcc_1v0"; 286*4882a593Smuzhiyun regulator-state-mem { 287*4882a593Smuzhiyun regulator-on-in-suspend; 288*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun vcc1v8_soc: LDO_REG2 { 293*4882a593Smuzhiyun regulator-always-on; 294*4882a593Smuzhiyun regulator-boot-on; 295*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 296*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun regulator-name = "vcc1v8_soc"; 299*4882a593Smuzhiyun regulator-state-mem { 300*4882a593Smuzhiyun regulator-on-in-suspend; 301*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 302*4882a593Smuzhiyun }; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun vdd1v0_soc: LDO_REG3 { 306*4882a593Smuzhiyun regulator-always-on; 307*4882a593Smuzhiyun regulator-boot-on; 308*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 309*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun regulator-name = "vcc1v0_soc"; 312*4882a593Smuzhiyun regulator-state-mem { 313*4882a593Smuzhiyun regulator-on-in-suspend; 314*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun vcc3v0_pmu: LDO_REG4 { 319*4882a593Smuzhiyun regulator-always-on; 320*4882a593Smuzhiyun regulator-boot-on; 321*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 322*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun regulator-name = "vcc3v0_pmu"; 325*4882a593Smuzhiyun regulator-state-mem { 326*4882a593Smuzhiyun regulator-on-in-suspend; 327*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 333*4882a593Smuzhiyun regulator-always-on; 334*4882a593Smuzhiyun regulator-boot-on; 335*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 336*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun regulator-name = "vccio_sd"; 339*4882a593Smuzhiyun regulator-state-mem { 340*4882a593Smuzhiyun regulator-on-in-suspend; 341*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun vcc_sd: LDO_REG6 { 346*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 347*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun regulator-name = "vcc_sd"; 350*4882a593Smuzhiyun regulator-state-mem { 351*4882a593Smuzhiyun regulator-on-in-suspend; 352*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun }; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG7 { 358*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 359*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 362*4882a593Smuzhiyun regulator-state-mem { 363*4882a593Smuzhiyun regulator-off-in-suspend; 364*4882a593Smuzhiyun regulator-suspend-microvolt = <2800000>; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 369*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 370*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 373*4882a593Smuzhiyun regulator-state-mem { 374*4882a593Smuzhiyun regulator-on-in-suspend; 375*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun vdd1v5_dvp: LDO_REG9 { 380*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 381*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun regulator-name = "vdd1v5_dvp"; 384*4882a593Smuzhiyun regulator-state-mem { 385*4882a593Smuzhiyun regulator-off-in-suspend; 386*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun dcdc_boost: BOOST { 391*4882a593Smuzhiyun regulator-always-on; 392*4882a593Smuzhiyun regulator-boot-on; 393*4882a593Smuzhiyun regulator-min-microvolt = <4700000>; 394*4882a593Smuzhiyun regulator-max-microvolt = <5400000>; 395*4882a593Smuzhiyun regulator-name = "boost"; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun otg_switch: OTG_SWITCH { 399*4882a593Smuzhiyun regulator-name = "otg_switch"; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun battery { 404*4882a593Smuzhiyun compatible = "rk817,battery"; 405*4882a593Smuzhiyun ocv_table = <3500 3625 3685 3697 3718 3735 3748 406*4882a593Smuzhiyun 3760 3774 3788 3802 3816 3834 3853 407*4882a593Smuzhiyun 3877 3908 3946 3975 4018 4071 4106>; 408*4882a593Smuzhiyun design_capacity = <2500>; 409*4882a593Smuzhiyun design_qmax = <2750>; 410*4882a593Smuzhiyun bat_res = <100>; 411*4882a593Smuzhiyun sleep_enter_current = <300>; 412*4882a593Smuzhiyun sleep_exit_current = <300>; 413*4882a593Smuzhiyun sleep_filter_current = <100>; 414*4882a593Smuzhiyun power_off_thresd = <3500>; 415*4882a593Smuzhiyun zero_algorithm_vol = <3850>; 416*4882a593Smuzhiyun max_soc_offset = <60>; 417*4882a593Smuzhiyun monitor_sec = <5>; 418*4882a593Smuzhiyun sample_res = <10>; 419*4882a593Smuzhiyun virtual_power = <1>; 420*4882a593Smuzhiyun }; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun charger { 423*4882a593Smuzhiyun compatible = "rk817,charger"; 424*4882a593Smuzhiyun min_input_voltage = <4500>; 425*4882a593Smuzhiyun max_input_current = <1500>; 426*4882a593Smuzhiyun max_chrg_current = <2000>; 427*4882a593Smuzhiyun max_chrg_voltage = <4200>; 428*4882a593Smuzhiyun chrg_term_mode = <0>; 429*4882a593Smuzhiyun chrg_finish_cur = <300>; 430*4882a593Smuzhiyun virtual_power = <0>; 431*4882a593Smuzhiyun dc_det_adc = <0>; 432*4882a593Smuzhiyun extcon = <&u2phy>; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun rk817_codec: codec { 436*4882a593Smuzhiyun #sound-dai-cells = <0>; 437*4882a593Smuzhiyun compatible = "rockchip,rk817-codec"; 438*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>; 439*4882a593Smuzhiyun clock-names = "mclk"; 440*4882a593Smuzhiyun pinctrl-names = "default"; 441*4882a593Smuzhiyun pinctrl-0 = <&i2s1_2ch_mclk>; 442*4882a593Smuzhiyun hp-volume = <20>; 443*4882a593Smuzhiyun spk-volume = <3>; 444*4882a593Smuzhiyun status = "okay"; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun}; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun&i2c2 { 450*4882a593Smuzhiyun status = "okay"; 451*4882a593Smuzhiyun clock-frequency = <400000>; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun /* 24M mclk is shared for multiple cameras */ 454*4882a593Smuzhiyun pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun /* These are relatively safe rise/fall times; TODO: measure */ 457*4882a593Smuzhiyun i2c-scl-falling-time-ns = <50>; 458*4882a593Smuzhiyun i2c-scl-rising-time-ns = <300>; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun gc2155: gc2155@3c { 461*4882a593Smuzhiyun compatible = "gc,gc2155"; 462*4882a593Smuzhiyun reg = <0x3c>; 463*4882a593Smuzhiyun pinctrl-names = "default"; 464*4882a593Smuzhiyun pinctrl-0 = <&cif_pin_m0>; 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 467*4882a593Smuzhiyun clock-names = "xvclk"; 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 470*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 471*4882a593Smuzhiyun dvdd-supply = <&vcc1v8_dvp>; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun /* hw changed the pwdn to gpio2_b5 */ 474*4882a593Smuzhiyun pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun port { 477*4882a593Smuzhiyun gc2155_out: endpoint { 478*4882a593Smuzhiyun remote-endpoint = <&cif_in>; 479*4882a593Smuzhiyun }; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun ov5695: ov5695@36 { 484*4882a593Smuzhiyun compatible = "ovti,ov5695"; 485*4882a593Smuzhiyun reg = <0x36>; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 488*4882a593Smuzhiyun clock-names = "xvclk"; 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 491*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 492*4882a593Smuzhiyun dvdd-supply = <&vcc1v8_dvp>; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ 495*4882a593Smuzhiyun pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun port { 498*4882a593Smuzhiyun ucam_out: endpoint { 499*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam>; 500*4882a593Smuzhiyun data-lanes = <1 2>; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun}; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun&i2s1_2ch { 507*4882a593Smuzhiyun status = "okay"; 508*4882a593Smuzhiyun #sound-dai-cells = <0>; 509*4882a593Smuzhiyun}; 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun&io_domains { 512*4882a593Smuzhiyun status = "okay"; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun vccio1-supply = <&vcc1v8_soc>; 515*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 516*4882a593Smuzhiyun vccio3-supply = <&vcc1v8_dvp>; 517*4882a593Smuzhiyun vccio4-supply = <&vcc_3v0>; 518*4882a593Smuzhiyun vccio5-supply = <&vcc_3v0>; 519*4882a593Smuzhiyun}; 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun&isp_mmu { 522*4882a593Smuzhiyun status = "okay"; 523*4882a593Smuzhiyun}; 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun&mipi_dphy_rx0 { 526*4882a593Smuzhiyun status = "okay"; 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun ports { 529*4882a593Smuzhiyun #address-cells = <1>; 530*4882a593Smuzhiyun #size-cells = <0>; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun port@0 { 533*4882a593Smuzhiyun reg = <0>; 534*4882a593Smuzhiyun #address-cells = <1>; 535*4882a593Smuzhiyun #size-cells = <0>; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun mipi_in_ucam: endpoint@1 { 538*4882a593Smuzhiyun reg = <1>; 539*4882a593Smuzhiyun remote-endpoint = <&ucam_out>; 540*4882a593Smuzhiyun data-lanes = <1 2>; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun }; 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun port@1 { 545*4882a593Smuzhiyun reg = <1>; 546*4882a593Smuzhiyun #address-cells = <1>; 547*4882a593Smuzhiyun #size-cells = <0>; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun dphy_rx0_out: endpoint@0 { 550*4882a593Smuzhiyun reg = <0>; 551*4882a593Smuzhiyun remote-endpoint = <&isp0_mipi_in>; 552*4882a593Smuzhiyun }; 553*4882a593Smuzhiyun }; 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun}; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun&nandc0 { 558*4882a593Smuzhiyun status = "okay"; 559*4882a593Smuzhiyun}; 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun&rkisp1 { 562*4882a593Smuzhiyun status = "okay"; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun port { 565*4882a593Smuzhiyun #address-cells = <1>; 566*4882a593Smuzhiyun #size-cells = <0>; 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun isp0_mipi_in: endpoint@0 { 569*4882a593Smuzhiyun reg = <0>; 570*4882a593Smuzhiyun remote-endpoint = <&dphy_rx0_out>; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun }; 573*4882a593Smuzhiyun}; 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun&pmu_io_domains { 576*4882a593Smuzhiyun status = "okay"; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun pmuio1-supply = <&vcc3v0_pmu>; 579*4882a593Smuzhiyun pmuio2-supply = <&vcc3v0_pmu>; 580*4882a593Smuzhiyun}; 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun&rk_rga { 583*4882a593Smuzhiyun status = "okay"; 584*4882a593Smuzhiyun}; 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun&saradc { 587*4882a593Smuzhiyun status = "okay"; 588*4882a593Smuzhiyun vref-supply = <&vcc1v8_soc>; 589*4882a593Smuzhiyun}; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun&sdmmc { 592*4882a593Smuzhiyun bus-width = <4>; 593*4882a593Smuzhiyun cap-mmc-highspeed; 594*4882a593Smuzhiyun cap-sd-highspeed; 595*4882a593Smuzhiyun no-sdio; 596*4882a593Smuzhiyun no-mmc; 597*4882a593Smuzhiyun card-detect-delay = <800>; 598*4882a593Smuzhiyun ignore-pm-notify; 599*4882a593Smuzhiyun /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ 600*4882a593Smuzhiyun sd-uhs-sdr12; 601*4882a593Smuzhiyun sd-uhs-sdr25; 602*4882a593Smuzhiyun sd-uhs-sdr50; 603*4882a593Smuzhiyun sd-uhs-sdr104; 604*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 605*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 606*4882a593Smuzhiyun status = "disabled"; 607*4882a593Smuzhiyun}; 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun&sdio { 610*4882a593Smuzhiyun bus-width = <4>; 611*4882a593Smuzhiyun cap-sd-highspeed; 612*4882a593Smuzhiyun no-sd; 613*4882a593Smuzhiyun no-mmc; 614*4882a593Smuzhiyun ignore-pm-notify; 615*4882a593Smuzhiyun keep-power-in-suspend; 616*4882a593Smuzhiyun non-removable; 617*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 618*4882a593Smuzhiyun sd-uhs-sdr104; 619*4882a593Smuzhiyun status = "okay"; 620*4882a593Smuzhiyun}; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun&tsadc { 623*4882a593Smuzhiyun pinctrl-names = "init", "default"; 624*4882a593Smuzhiyun pinctrl-0 = <&tsadc_otp_gpio>; 625*4882a593Smuzhiyun pinctrl-1 = <&tsadc_otp_out>; 626*4882a593Smuzhiyun status = "okay"; 627*4882a593Smuzhiyun}; 628*4882a593Smuzhiyun 629*4882a593Smuzhiyun&u2phy { 630*4882a593Smuzhiyun status = "okay"; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun u2phy_host: host-port { 633*4882a593Smuzhiyun status = "okay"; 634*4882a593Smuzhiyun }; 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun u2phy_otg: otg-port { 637*4882a593Smuzhiyun status = "okay"; 638*4882a593Smuzhiyun }; 639*4882a593Smuzhiyun}; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun&usb20_otg { 642*4882a593Smuzhiyun status = "okay"; 643*4882a593Smuzhiyun}; 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun&uart1 { 646*4882a593Smuzhiyun pinctrl-names = "default"; 647*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer &uart1_cts>; 648*4882a593Smuzhiyun status = "okay"; 649*4882a593Smuzhiyun}; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun&vip_mmu { 652*4882a593Smuzhiyun status = "okay"; 653*4882a593Smuzhiyun}; 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun&mpp_srv { 656*4882a593Smuzhiyun status = "okay"; 657*4882a593Smuzhiyun}; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun&vdpu { 660*4882a593Smuzhiyun status = "okay"; 661*4882a593Smuzhiyun}; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun&vepu { 664*4882a593Smuzhiyun status = "okay"; 665*4882a593Smuzhiyun}; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun&vpu_mmu { 668*4882a593Smuzhiyun status = "okay"; 669*4882a593Smuzhiyun}; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun&hevc { 672*4882a593Smuzhiyun status = "okay"; 673*4882a593Smuzhiyun}; 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun&hevc_mmu { 676*4882a593Smuzhiyun status = "okay"; 677*4882a593Smuzhiyun}; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun&pinctrl { 680*4882a593Smuzhiyun cif-pin-m0 { 681*4882a593Smuzhiyun cif_pin_m0: cif-pin-m0 { 682*4882a593Smuzhiyun rockchip,pins = 683*4882a593Smuzhiyun <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */ 684*4882a593Smuzhiyun <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */ 685*4882a593Smuzhiyun <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */ 686*4882a593Smuzhiyun <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */ 687*4882a593Smuzhiyun <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */ 688*4882a593Smuzhiyun <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */ 689*4882a593Smuzhiyun <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */ 690*4882a593Smuzhiyun <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */ 691*4882a593Smuzhiyun <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */ 692*4882a593Smuzhiyun <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */ 693*4882a593Smuzhiyun <2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */ 694*4882a593Smuzhiyun }; 695*4882a593Smuzhiyun }; 696*4882a593Smuzhiyun 697*4882a593Smuzhiyun pmic { 698*4882a593Smuzhiyun pmic_int: pmic_int { 699*4882a593Smuzhiyun rockchip,pins = 700*4882a593Smuzhiyun <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 701*4882a593Smuzhiyun }; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 704*4882a593Smuzhiyun rockchip,pins = 705*4882a593Smuzhiyun <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 706*4882a593Smuzhiyun }; 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 709*4882a593Smuzhiyun rockchip,pins = 710*4882a593Smuzhiyun <0 RK_PA4 1 &pcfg_pull_none>; 711*4882a593Smuzhiyun }; 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 714*4882a593Smuzhiyun rockchip,pins = 715*4882a593Smuzhiyun <0 RK_PA4 2 &pcfg_pull_none>; 716*4882a593Smuzhiyun }; 717*4882a593Smuzhiyun }; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun sdio-pwrseq { 720*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 721*4882a593Smuzhiyun rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun }; 724*4882a593Smuzhiyun}; 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 727*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 728*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 729