1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "rk3326.dtsi" 8*4882a593Smuzhiyun#include "px30-android.dtsi" 9*4882a593Smuzhiyun#include "rk3326-evb-lp3-v10.dtsi" 10*4882a593Smuzhiyun#include "rk3326-863-cif-sensor.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip rk3326 evb board"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3326-evb-lp3-v10-avb", "rockchip,rk3326"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&i2c2 { 18*4882a593Smuzhiyun status = "okay"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun clock-frequency = <100000>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* These are relatively safe rise/fall times; TODO: measure */ 23*4882a593Smuzhiyun i2c-scl-falling-time-ns = <50>; 24*4882a593Smuzhiyun i2c-scl-rising-time-ns = <300>; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun ov5695: ov5695@36 { 27*4882a593Smuzhiyun compatible = "ovti,ov5695"; 28*4882a593Smuzhiyun reg = <0x36>; 29*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 30*4882a593Smuzhiyun clock-names = "xvclk"; 31*4882a593Smuzhiyun /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ 32*4882a593Smuzhiyun pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 33*4882a593Smuzhiyun //pinctrl-names = "default"; 34*4882a593Smuzhiyun //pinctrl-0 = <&cif_clkout_m0>; 35*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 36*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 37*4882a593Smuzhiyun rockchip,camera-module-name = "TongJu"; 38*4882a593Smuzhiyun rockchip,camera-module-lens-name = "CHT842-MD"; 39*4882a593Smuzhiyun port { 40*4882a593Smuzhiyun ov5695_out: endpoint { 41*4882a593Smuzhiyun remote-endpoint = <&mipi_in>; 42*4882a593Smuzhiyun data-lanes = <1 2>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&mipi_dphy_rx0 { 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun ports { 52*4882a593Smuzhiyun #address-cells = <1>; 53*4882a593Smuzhiyun #size-cells = <0>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun port@0 { 56*4882a593Smuzhiyun reg = <0>; 57*4882a593Smuzhiyun #address-cells = <1>; 58*4882a593Smuzhiyun #size-cells = <0>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun mipi_in: endpoint@1 { 61*4882a593Smuzhiyun reg = <1>; 62*4882a593Smuzhiyun remote-endpoint = <&ov5695_out>; 63*4882a593Smuzhiyun data-lanes = <1 2>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun port@1 { 68*4882a593Smuzhiyun reg = <1>; 69*4882a593Smuzhiyun #address-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <0>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun dphy_rx_out: endpoint@0 { 73*4882a593Smuzhiyun reg = <0>; 74*4882a593Smuzhiyun remote-endpoint = <&isp_mipi_in>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&rkisp1 { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun pinctrl-names = "default"; 83*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout_m0 &dvp_d2d9_m0>; 84*4882a593Smuzhiyun port { 85*4882a593Smuzhiyun #address-cells = <1>; 86*4882a593Smuzhiyun #size-cells = <0>; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun isp_mipi_in: endpoint@0 { 89*4882a593Smuzhiyun reg = <0>; 90*4882a593Smuzhiyun remote-endpoint = <&dphy_rx_out>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95