1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 11*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 12*4882a593Smuzhiyun#include "rk3326.dtsi" 13*4882a593Smuzhiyun#include "rk3326-863-cif-sensor.dtsi" 14*4882a593Smuzhiyun#include "px30-android.dtsi" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun adc-keys { 18*4882a593Smuzhiyun compatible = "adc-keys"; 19*4882a593Smuzhiyun io-channels = <&saradc 2>; 20*4882a593Smuzhiyun io-channel-names = "buttons"; 21*4882a593Smuzhiyun poll-interval = <100>; 22*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun vol-down-key { 25*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 26*4882a593Smuzhiyun label = "volume down"; 27*4882a593Smuzhiyun press-threshold-microvolt = <300000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun vol-up-key { 31*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 32*4882a593Smuzhiyun label = "volume up"; 33*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun backlight: backlight { 38*4882a593Smuzhiyun compatible = "pwm-backlight"; 39*4882a593Smuzhiyun pwms = <&pwm1 0 25000 0>; 40*4882a593Smuzhiyun brightness-levels = < 41*4882a593Smuzhiyun 0 10 10 11 11 12 12 13 42*4882a593Smuzhiyun 13 14 14 15 15 16 16 17 43*4882a593Smuzhiyun 17 18 18 19 20 21 22 23 44*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 45*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 46*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 47*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 48*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 49*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 50*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 51*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 52*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 53*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 54*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 55*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 56*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 57*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 58*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 59*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 60*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 61*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 62*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 63*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 64*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 65*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 66*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 67*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 68*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 69*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 70*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 71*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 72*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 73*4882a593Smuzhiyun default-brightness-level = <200>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun charge-animation { 77*4882a593Smuzhiyun compatible = "rockchip,uboot-charge"; 78*4882a593Smuzhiyun rockchip,uboot-charge-on = <1>; 79*4882a593Smuzhiyun rockchip,android-charge-on = <0>; 80*4882a593Smuzhiyun rockchip,uboot-low-power-voltage = <3500>; 81*4882a593Smuzhiyun rockchip,screen-on-voltage = <3600>; 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun rk817-sound { 86*4882a593Smuzhiyun compatible = "rockchip,multicodecs-card"; 87*4882a593Smuzhiyun rockchip,card-name = "rockchip-rk817"; 88*4882a593Smuzhiyun hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; 89*4882a593Smuzhiyun rockchip,format = "i2s"; 90*4882a593Smuzhiyun rockchip,mclk-fs = <256>; 91*4882a593Smuzhiyun rockchip,cpu = <&i2s1_2ch>; 92*4882a593Smuzhiyun rockchip,codec = <&rk817_codec>; 93*4882a593Smuzhiyun pinctrl-names = "default"; 94*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 98*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 99*4882a593Smuzhiyun clocks = <&cru SCLK_WIFI_PMU>; 100*4882a593Smuzhiyun clock-names = "clk_wifi_pmu"; 101*4882a593Smuzhiyun pinctrl-names = "default"; 102*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * On the module itself this is one of these (depending 106*4882a593Smuzhiyun * on the actual card populated): 107*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 108*4882a593Smuzhiyun * - PDN (power down when low) 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun vccsys: vccsys { 114*4882a593Smuzhiyun compatible = "regulator-fixed"; 115*4882a593Smuzhiyun regulator-name = "vcc3v8_sys"; 116*4882a593Smuzhiyun regulator-always-on; 117*4882a593Smuzhiyun regulator-boot-on; 118*4882a593Smuzhiyun regulator-min-microvolt = <3800000>; 119*4882a593Smuzhiyun regulator-max-microvolt = <3800000>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun wireless-wlan { 123*4882a593Smuzhiyun compatible = "wlan-platdata"; 124*4882a593Smuzhiyun wifi_chip_type = "rtl8723cs"; 125*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 126*4882a593Smuzhiyun WIFI,vbat_gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun wireless-bluetooth { 131*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 132*4882a593Smuzhiyun uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; 133*4882a593Smuzhiyun pinctrl-names = "default","rts_gpio"; 134*4882a593Smuzhiyun pinctrl-0 = <&uart1_rts>; 135*4882a593Smuzhiyun pinctrl-1 = <&uart1_rts_gpio>; 136*4882a593Smuzhiyun BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 137*4882a593Smuzhiyun BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; 138*4882a593Smuzhiyun BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun&display_subsystem { 145*4882a593Smuzhiyun status = "okay"; 146*4882a593Smuzhiyun}; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun&dsi { 149*4882a593Smuzhiyun status = "okay"; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun panel@0 { 152*4882a593Smuzhiyun compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi"; 153*4882a593Smuzhiyun reg = <0>; 154*4882a593Smuzhiyun backlight = <&backlight>; 155*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; 156*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 157*4882a593Smuzhiyun prepare-delay-ms = <20>; 158*4882a593Smuzhiyun reset-delay-ms = <20>; 159*4882a593Smuzhiyun init-delay-ms = <20>; 160*4882a593Smuzhiyun enable-delay-ms = <120>; 161*4882a593Smuzhiyun disable-delay-ms = <20>; 162*4882a593Smuzhiyun unprepare-delay-ms = <20>; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun width-mm = <108>; 165*4882a593Smuzhiyun height-mm = <172>; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 168*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 169*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 170*4882a593Smuzhiyun dsi,lanes = <4>; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun panel-init-sequence = [ 173*4882a593Smuzhiyun 05 78 01 11 174*4882a593Smuzhiyun 05 14 01 29 175*4882a593Smuzhiyun ]; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun panel-exit-sequence = [ 178*4882a593Smuzhiyun 05 00 01 28 179*4882a593Smuzhiyun 05 00 01 10 180*4882a593Smuzhiyun ]; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun display-timings { 183*4882a593Smuzhiyun native-mode = <&timing0>; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun timing0: timing0 { 186*4882a593Smuzhiyun clock-frequency = <66000000>; 187*4882a593Smuzhiyun hactive = <800>; 188*4882a593Smuzhiyun vactive = <1280>; 189*4882a593Smuzhiyun hfront-porch = <2>; 190*4882a593Smuzhiyun hsync-len = <18>; 191*4882a593Smuzhiyun hback-porch = <18>; 192*4882a593Smuzhiyun vfront-porch = <4>; 193*4882a593Smuzhiyun vsync-len = <4>; 194*4882a593Smuzhiyun vback-porch = <16>; 195*4882a593Smuzhiyun hsync-active = <0>; 196*4882a593Smuzhiyun vsync-active = <0>; 197*4882a593Smuzhiyun de-active = <0>; 198*4882a593Smuzhiyun pixelclk-active = <0>; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun ports { 203*4882a593Smuzhiyun #address-cells = <1>; 204*4882a593Smuzhiyun #size-cells = <0>; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun port@0 { 207*4882a593Smuzhiyun reg = <0>; 208*4882a593Smuzhiyun panel_in_dsi: endpoint { 209*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun ports { 216*4882a593Smuzhiyun #address-cells = <1>; 217*4882a593Smuzhiyun #size-cells = <0>; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun port@1 { 220*4882a593Smuzhiyun reg = <1>; 221*4882a593Smuzhiyun dsi_out_panel: endpoint { 222*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&dsi_in_vopb { 229*4882a593Smuzhiyun status = "okay"; 230*4882a593Smuzhiyun}; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun&route_dsi { 233*4882a593Smuzhiyun connect = <&vopb_out_dsi>; 234*4882a593Smuzhiyun status = "okay"; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&bus_apll { 238*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&cpu0 { 243*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 244*4882a593Smuzhiyun}; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun&cpu0_opp_table { 247*4882a593Smuzhiyun /* 248*4882a593Smuzhiyun * max IR-drop values on different freq condition for this board! 249*4882a593Smuzhiyun */ 250*4882a593Smuzhiyun rockchip,board-irdrop = < 251*4882a593Smuzhiyun /*MHz MHz uV */ 252*4882a593Smuzhiyun 0 815 37500 253*4882a593Smuzhiyun 816 1119 50000 254*4882a593Smuzhiyun 1200 1512 75000 255*4882a593Smuzhiyun >; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&dmc_opp_table { 259*4882a593Smuzhiyun /* 260*4882a593Smuzhiyun * max IR-drop values on different freq condition for this board! 261*4882a593Smuzhiyun */ 262*4882a593Smuzhiyun rockchip,board-irdrop = < 263*4882a593Smuzhiyun /*MHz MHz uV */ 264*4882a593Smuzhiyun 451 800 75000 265*4882a593Smuzhiyun >; 266*4882a593Smuzhiyun}; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun&dfi { 269*4882a593Smuzhiyun status = "okay"; 270*4882a593Smuzhiyun}; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun&dmc { 273*4882a593Smuzhiyun center-supply = <&vdd_logic>; 274*4882a593Smuzhiyun status = "okay"; 275*4882a593Smuzhiyun}; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun&emmc { 278*4882a593Smuzhiyun bus-width = <8>; 279*4882a593Smuzhiyun cap-mmc-highspeed; 280*4882a593Smuzhiyun mmc-hs200-1_8v; 281*4882a593Smuzhiyun no-sdio; 282*4882a593Smuzhiyun no-sd; 283*4882a593Smuzhiyun disable-wp; 284*4882a593Smuzhiyun non-removable; 285*4882a593Smuzhiyun num-slots = <1>; 286*4882a593Smuzhiyun status = "okay"; 287*4882a593Smuzhiyun}; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun&gpu { 290*4882a593Smuzhiyun mali-supply = <&vdd_logic>; 291*4882a593Smuzhiyun status = "okay"; 292*4882a593Smuzhiyun}; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun&i2c0 { 295*4882a593Smuzhiyun status = "okay"; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun rk817: pmic@20 { 298*4882a593Smuzhiyun compatible = "rockchip,rk817"; 299*4882a593Smuzhiyun reg = <0x20>; 300*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 301*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 302*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 303*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 304*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 305*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 306*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 307*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 308*4882a593Smuzhiyun rockchip,system-power-controller; 309*4882a593Smuzhiyun wakeup-source; 310*4882a593Smuzhiyun #clock-cells = <1>; 311*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 312*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 313*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 314*4882a593Smuzhiyun pmic-reset-func = <1>; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun vcc1-supply = <&vccsys>; 317*4882a593Smuzhiyun vcc2-supply = <&vccsys>; 318*4882a593Smuzhiyun vcc3-supply = <&vccsys>; 319*4882a593Smuzhiyun vcc4-supply = <&vccsys>; 320*4882a593Smuzhiyun vcc5-supply = <&vccsys>; 321*4882a593Smuzhiyun vcc6-supply = <&vccsys>; 322*4882a593Smuzhiyun vcc7-supply = <&vcc_3v0>; 323*4882a593Smuzhiyun vcc8-supply = <&vccsys>; 324*4882a593Smuzhiyun vcc9-supply = <&dcdc_boost>; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun pwrkey { 327*4882a593Smuzhiyun status = "okay"; 328*4882a593Smuzhiyun }; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 331*4882a593Smuzhiyun gpio-controller; 332*4882a593Smuzhiyun #gpio-cells = <2>; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun rk817_ts_gpio1: rk817_ts_gpio1 { 335*4882a593Smuzhiyun pins = "gpio_ts"; 336*4882a593Smuzhiyun function = "pin_fun1"; 337*4882a593Smuzhiyun /* output-low; */ 338*4882a593Smuzhiyun /* input-enable; */ 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun rk817_gt_gpio2: rk817_gt_gpio2 { 342*4882a593Smuzhiyun pins = "gpio_gt"; 343*4882a593Smuzhiyun function = "pin_fun1"; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun rk817_pin_ts: rk817_pin_ts { 347*4882a593Smuzhiyun pins = "gpio_ts"; 348*4882a593Smuzhiyun function = "pin_fun0"; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun rk817_pin_gt: rk817_pin_gt { 352*4882a593Smuzhiyun pins = "gpio_gt"; 353*4882a593Smuzhiyun function = "pin_fun0"; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 357*4882a593Smuzhiyun pins = "gpio_slp"; 358*4882a593Smuzhiyun function = "pin_fun0"; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 362*4882a593Smuzhiyun pins = "gpio_slp"; 363*4882a593Smuzhiyun function = "pin_fun1"; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 367*4882a593Smuzhiyun pins = "gpio_slp"; 368*4882a593Smuzhiyun function = "pin_fun2"; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 372*4882a593Smuzhiyun pins = "gpio_slp"; 373*4882a593Smuzhiyun function = "pin_fun3"; 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun }; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun regulators { 378*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 379*4882a593Smuzhiyun regulator-always-on; 380*4882a593Smuzhiyun regulator-boot-on; 381*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 382*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 383*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 384*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 385*4882a593Smuzhiyun regulator-name = "vdd_logic"; 386*4882a593Smuzhiyun regulator-state-mem { 387*4882a593Smuzhiyun regulator-on-in-suspend; 388*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 393*4882a593Smuzhiyun regulator-always-on; 394*4882a593Smuzhiyun regulator-boot-on; 395*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 396*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 397*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 398*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 399*4882a593Smuzhiyun regulator-name = "vdd_arm"; 400*4882a593Smuzhiyun regulator-state-mem { 401*4882a593Smuzhiyun regulator-off-in-suspend; 402*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 407*4882a593Smuzhiyun regulator-always-on; 408*4882a593Smuzhiyun regulator-boot-on; 409*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 410*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 411*4882a593Smuzhiyun regulator-state-mem { 412*4882a593Smuzhiyun regulator-on-in-suspend; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun vcc_3v0: DCDC_REG4 { 417*4882a593Smuzhiyun regulator-always-on; 418*4882a593Smuzhiyun regulator-boot-on; 419*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 420*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 421*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 422*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 423*4882a593Smuzhiyun regulator-state-mem { 424*4882a593Smuzhiyun regulator-on-in-suspend; 425*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun vcc_1v0: LDO_REG1 { 430*4882a593Smuzhiyun regulator-always-on; 431*4882a593Smuzhiyun regulator-boot-on; 432*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 433*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 434*4882a593Smuzhiyun regulator-name = "vcc_1v0"; 435*4882a593Smuzhiyun regulator-state-mem { 436*4882a593Smuzhiyun regulator-on-in-suspend; 437*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun }; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun vcc1v8_soc: LDO_REG2 { 442*4882a593Smuzhiyun regulator-always-on; 443*4882a593Smuzhiyun regulator-boot-on; 444*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 445*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun regulator-name = "vcc1v8_soc"; 448*4882a593Smuzhiyun regulator-state-mem { 449*4882a593Smuzhiyun regulator-on-in-suspend; 450*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun vdd1v0_soc: LDO_REG3 { 455*4882a593Smuzhiyun regulator-always-on; 456*4882a593Smuzhiyun regulator-boot-on; 457*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 458*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun regulator-name = "vcc1v0_soc"; 461*4882a593Smuzhiyun regulator-state-mem { 462*4882a593Smuzhiyun regulator-on-in-suspend; 463*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun vcc3v0_pmu: LDO_REG4 { 468*4882a593Smuzhiyun regulator-always-on; 469*4882a593Smuzhiyun regulator-boot-on; 470*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 471*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun regulator-name = "vcc3v0_pmu"; 474*4882a593Smuzhiyun regulator-state-mem { 475*4882a593Smuzhiyun regulator-on-in-suspend; 476*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun }; 479*4882a593Smuzhiyun }; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 482*4882a593Smuzhiyun regulator-always-on; 483*4882a593Smuzhiyun regulator-boot-on; 484*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 485*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 486*4882a593Smuzhiyun 487*4882a593Smuzhiyun regulator-name = "vccio_sd"; 488*4882a593Smuzhiyun regulator-state-mem { 489*4882a593Smuzhiyun regulator-on-in-suspend; 490*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun vcc_sd: LDO_REG6 { 495*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 496*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun regulator-name = "vcc_sd"; 499*4882a593Smuzhiyun regulator-state-mem { 500*4882a593Smuzhiyun regulator-on-in-suspend; 501*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG7 { 507*4882a593Smuzhiyun regulator-boot-on; 508*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 509*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 510*4882a593Smuzhiyun 511*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 512*4882a593Smuzhiyun regulator-state-mem { 513*4882a593Smuzhiyun regulator-off-in-suspend; 514*4882a593Smuzhiyun regulator-suspend-microvolt = <2800000>; 515*4882a593Smuzhiyun }; 516*4882a593Smuzhiyun }; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 519*4882a593Smuzhiyun regulator-boot-on; 520*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 521*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 524*4882a593Smuzhiyun regulator-state-mem { 525*4882a593Smuzhiyun regulator-off-in-suspend; 526*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun }; 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun vdd1v5_dvp: LDO_REG9 { 531*4882a593Smuzhiyun regulator-boot-on; 532*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 533*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun regulator-name = "vdd1v5_dvp"; 536*4882a593Smuzhiyun regulator-state-mem { 537*4882a593Smuzhiyun regulator-off-in-suspend; 538*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun dcdc_boost: BOOST { 543*4882a593Smuzhiyun regulator-always-on; 544*4882a593Smuzhiyun regulator-boot-on; 545*4882a593Smuzhiyun regulator-min-microvolt = <4700000>; 546*4882a593Smuzhiyun regulator-max-microvolt = <5400000>; 547*4882a593Smuzhiyun regulator-name = "boost"; 548*4882a593Smuzhiyun }; 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun otg_switch: OTG_SWITCH { 551*4882a593Smuzhiyun regulator-name = "otg_switch"; 552*4882a593Smuzhiyun }; 553*4882a593Smuzhiyun }; 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun battery { 556*4882a593Smuzhiyun compatible = "rk817,battery"; 557*4882a593Smuzhiyun ocv_table = <3500 3548 3592 3636 3687 3740 3780 558*4882a593Smuzhiyun 3806 3827 3846 3864 3889 3929 3964 559*4882a593Smuzhiyun 3993 4015 4030 4041 4056 4076 4148>; 560*4882a593Smuzhiyun design_capacity = <4000>; 561*4882a593Smuzhiyun design_qmax = <4200>; 562*4882a593Smuzhiyun bat_res = <100>; 563*4882a593Smuzhiyun sleep_enter_current = <150>; 564*4882a593Smuzhiyun sleep_exit_current = <180>; 565*4882a593Smuzhiyun sleep_filter_current = <100>; 566*4882a593Smuzhiyun power_off_thresd = <3500>; 567*4882a593Smuzhiyun zero_algorithm_vol = <3850>; 568*4882a593Smuzhiyun max_soc_offset = <60>; 569*4882a593Smuzhiyun monitor_sec = <5>; 570*4882a593Smuzhiyun sample_res = <10>; 571*4882a593Smuzhiyun virtual_power = <0>; 572*4882a593Smuzhiyun }; 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun charger { 575*4882a593Smuzhiyun compatible = "rk817,charger"; 576*4882a593Smuzhiyun min_input_voltage = <4500>; 577*4882a593Smuzhiyun max_input_current = <1500>; 578*4882a593Smuzhiyun max_chrg_current = <2000>; 579*4882a593Smuzhiyun max_chrg_voltage = <4200>; 580*4882a593Smuzhiyun chrg_term_mode = <0>; 581*4882a593Smuzhiyun chrg_finish_cur = <300>; 582*4882a593Smuzhiyun virtual_power = <0>; 583*4882a593Smuzhiyun dc_det_adc = <0>; 584*4882a593Smuzhiyun extcon = <&u2phy>; 585*4882a593Smuzhiyun }; 586*4882a593Smuzhiyun 587*4882a593Smuzhiyun rk817_codec: codec { 588*4882a593Smuzhiyun #sound-dai-cells = <0>; 589*4882a593Smuzhiyun compatible = "rockchip,rk817-codec"; 590*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>; 591*4882a593Smuzhiyun clock-names = "mclk"; 592*4882a593Smuzhiyun pinctrl-names = "default"; 593*4882a593Smuzhiyun pinctrl-0 = <&i2s1_2ch_mclk>; 594*4882a593Smuzhiyun hp-volume = <20>; 595*4882a593Smuzhiyun spk-volume = <3>; 596*4882a593Smuzhiyun mic-in-differential; 597*4882a593Smuzhiyun status = "okay"; 598*4882a593Smuzhiyun }; 599*4882a593Smuzhiyun }; 600*4882a593Smuzhiyun}; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun&i2c1 { 603*4882a593Smuzhiyun status = "okay"; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun ts@40 { 606*4882a593Smuzhiyun status = "okay"; 607*4882a593Smuzhiyun compatible = "GSL,GSL3673_800X1280"; 608*4882a593Smuzhiyun reg = <0x40>; 609*4882a593Smuzhiyun irq_gpio_number = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; 610*4882a593Smuzhiyun rst_gpio_number = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; 611*4882a593Smuzhiyun }; 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun sensor@19 { 614*4882a593Smuzhiyun status = "okay"; 615*4882a593Smuzhiyun compatible = "gs_lis3dh"; 616*4882a593Smuzhiyun reg = <0x19>; 617*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 618*4882a593Smuzhiyun irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; 619*4882a593Smuzhiyun irq_enable = <0>; 620*4882a593Smuzhiyun poll_delay_ms = <30>; 621*4882a593Smuzhiyun layout = <7>; 622*4882a593Smuzhiyun reprobe_en = <1>; 623*4882a593Smuzhiyun }; 624*4882a593Smuzhiyun}; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun&i2c2 { 627*4882a593Smuzhiyun status = "okay"; 628*4882a593Smuzhiyun}; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun&i2s1_2ch { 631*4882a593Smuzhiyun status = "okay"; 632*4882a593Smuzhiyun #sound-dai-cells = <0>; 633*4882a593Smuzhiyun}; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun&io_domains { 636*4882a593Smuzhiyun status = "okay"; 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun vccio1-supply = <&vcc_3v0>; 639*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 640*4882a593Smuzhiyun vccio3-supply = <&vcc2v8_dvp>; 641*4882a593Smuzhiyun vccio4-supply = <&vcc_3v0>; 642*4882a593Smuzhiyun vccio5-supply = <&vcc_3v0>; 643*4882a593Smuzhiyun}; 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun&nandc0 { 646*4882a593Smuzhiyun status = "okay"; 647*4882a593Smuzhiyun}; 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun&pinctrl { 650*4882a593Smuzhiyun headphone { 651*4882a593Smuzhiyun hp_det: hp-det { 652*4882a593Smuzhiyun rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; 653*4882a593Smuzhiyun }; 654*4882a593Smuzhiyun }; 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun pmic { 657*4882a593Smuzhiyun pmic_int: pmic_int { 658*4882a593Smuzhiyun rockchip,pins = 659*4882a593Smuzhiyun <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 660*4882a593Smuzhiyun }; 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 663*4882a593Smuzhiyun rockchip,pins = 664*4882a593Smuzhiyun <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 665*4882a593Smuzhiyun }; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 668*4882a593Smuzhiyun rockchip,pins = 669*4882a593Smuzhiyun <0 RK_PA4 1 &pcfg_pull_none>; 670*4882a593Smuzhiyun }; 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 673*4882a593Smuzhiyun rockchip,pins = 674*4882a593Smuzhiyun <0 RK_PA4 2 &pcfg_pull_none>; 675*4882a593Smuzhiyun }; 676*4882a593Smuzhiyun }; 677*4882a593Smuzhiyun 678*4882a593Smuzhiyun sdio-pwrseq { 679*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 680*4882a593Smuzhiyun rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 681*4882a593Smuzhiyun }; 682*4882a593Smuzhiyun }; 683*4882a593Smuzhiyun}; 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun&pmu_io_domains { 686*4882a593Smuzhiyun status = "okay"; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun pmuio1-supply = <&vcc3v0_pmu>; 689*4882a593Smuzhiyun pmuio2-supply = <&vcc3v0_pmu>; 690*4882a593Smuzhiyun}; 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun&pwm1 { 693*4882a593Smuzhiyun status = "okay"; 694*4882a593Smuzhiyun}; 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun&rk_rga { 697*4882a593Smuzhiyun status = "okay"; 698*4882a593Smuzhiyun}; 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun&rockchip_suspend { 701*4882a593Smuzhiyun status = "okay"; 702*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 703*4882a593Smuzhiyun}; 704*4882a593Smuzhiyun 705*4882a593Smuzhiyun&saradc { 706*4882a593Smuzhiyun status = "okay"; 707*4882a593Smuzhiyun vref-supply = <&vcc1v8_soc>; 708*4882a593Smuzhiyun}; 709*4882a593Smuzhiyun 710*4882a593Smuzhiyun&sdmmc { 711*4882a593Smuzhiyun bus-width = <4>; 712*4882a593Smuzhiyun cap-mmc-highspeed; 713*4882a593Smuzhiyun cap-sd-highspeed; 714*4882a593Smuzhiyun no-sdio; 715*4882a593Smuzhiyun no-mmc; 716*4882a593Smuzhiyun card-detect-delay = <800>; 717*4882a593Smuzhiyun ignore-pm-notify; 718*4882a593Smuzhiyun sd-uhs-sdr12; 719*4882a593Smuzhiyun sd-uhs-sdr25; 720*4882a593Smuzhiyun sd-uhs-sdr50; 721*4882a593Smuzhiyun sd-uhs-sdr104; 722*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 723*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 724*4882a593Smuzhiyun status = "disabled"; 725*4882a593Smuzhiyun}; 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun&sdio { 728*4882a593Smuzhiyun bus-width = <4>; 729*4882a593Smuzhiyun cap-sd-highspeed; 730*4882a593Smuzhiyun no-sd; 731*4882a593Smuzhiyun no-mmc; 732*4882a593Smuzhiyun ignore-pm-notify; 733*4882a593Smuzhiyun keep-power-in-suspend; 734*4882a593Smuzhiyun non-removable; 735*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 736*4882a593Smuzhiyun sd-uhs-sdr104; 737*4882a593Smuzhiyun status = "okay"; 738*4882a593Smuzhiyun}; 739*4882a593Smuzhiyun 740*4882a593Smuzhiyun&tsadc { 741*4882a593Smuzhiyun pinctrl-names = "gpio", "otpout"; 742*4882a593Smuzhiyun pinctrl-0 = <&tsadc_otp_gpio>; 743*4882a593Smuzhiyun pinctrl-1 = <&tsadc_otp_out>; 744*4882a593Smuzhiyun status = "okay"; 745*4882a593Smuzhiyun}; 746*4882a593Smuzhiyun 747*4882a593Smuzhiyun&u2phy { 748*4882a593Smuzhiyun status = "okay"; 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun u2phy_host: host-port { 751*4882a593Smuzhiyun rockchip,low-power-mode; 752*4882a593Smuzhiyun status = "okay"; 753*4882a593Smuzhiyun }; 754*4882a593Smuzhiyun 755*4882a593Smuzhiyun u2phy_otg: otg-port { 756*4882a593Smuzhiyun rockchip,low-power-mode; 757*4882a593Smuzhiyun status = "okay"; 758*4882a593Smuzhiyun }; 759*4882a593Smuzhiyun}; 760*4882a593Smuzhiyun 761*4882a593Smuzhiyun&usb20_otg { 762*4882a593Smuzhiyun status = "okay"; 763*4882a593Smuzhiyun}; 764*4882a593Smuzhiyun 765*4882a593Smuzhiyun&uart1 { 766*4882a593Smuzhiyun pinctrl-names = "default"; 767*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer &uart1_cts>; 768*4882a593Smuzhiyun status = "okay"; 769*4882a593Smuzhiyun}; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun&vip_mmu { 772*4882a593Smuzhiyun status = "okay"; 773*4882a593Smuzhiyun}; 774*4882a593Smuzhiyun 775*4882a593Smuzhiyun&vopb { 776*4882a593Smuzhiyun status = "okay"; 777*4882a593Smuzhiyun}; 778*4882a593Smuzhiyun 779*4882a593Smuzhiyun&vopb_mmu { 780*4882a593Smuzhiyun status = "okay"; 781*4882a593Smuzhiyun}; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun&mpp_srv { 784*4882a593Smuzhiyun status = "okay"; 785*4882a593Smuzhiyun}; 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun&vdpu { 788*4882a593Smuzhiyun status = "okay"; 789*4882a593Smuzhiyun}; 790*4882a593Smuzhiyun 791*4882a593Smuzhiyun&vepu { 792*4882a593Smuzhiyun status = "okay"; 793*4882a593Smuzhiyun}; 794*4882a593Smuzhiyun 795*4882a593Smuzhiyun&vpu_mmu { 796*4882a593Smuzhiyun status = "okay"; 797*4882a593Smuzhiyun}; 798*4882a593Smuzhiyun 799*4882a593Smuzhiyun&hevc { 800*4882a593Smuzhiyun status = "okay"; 801*4882a593Smuzhiyun}; 802*4882a593Smuzhiyun 803*4882a593Smuzhiyun&hevc_mmu { 804*4882a593Smuzhiyun status = "okay"; 805*4882a593Smuzhiyun}; 806