1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "rk3326-863-lp3-v10.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Rockchip rk3326 863 rkisp1 board"; 11*4882a593Smuzhiyun compatible = "rockchip,rk3326-863-lp3-v10-rkisp1", "rockchip,rk3326"; 12*4882a593Smuzhiyun}; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun&chosen { 15*4882a593Smuzhiyun bootargs_ext = "androidboot.boot_devices=ff390000.dwmmc,ff3b0000.nandc"; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&i2c2 { 19*4882a593Smuzhiyun status = "okay"; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun gc0312: gc0312@21 { 22*4882a593Smuzhiyun status = "okay"; 23*4882a593Smuzhiyun compatible = "galaxycore,gc0312"; 24*4882a593Smuzhiyun reg = <0x21>; 25*4882a593Smuzhiyun //pinctrl-names = "default"; 26*4882a593Smuzhiyun //pinctrl-0 = <&cif_clkout_m0>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 29*4882a593Smuzhiyun clock-names = "xvclk"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 32*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 33*4882a593Smuzhiyun dvdd-supply = <&vcc1v8_dvp>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 36*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 37*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 38*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 39*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan"; 40*4882a593Smuzhiyun port { 41*4882a593Smuzhiyun gc0312_out: endpoint { 42*4882a593Smuzhiyun remote-endpoint = <&dvp_in_fcam>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun gc2145: gc2145@3c { 48*4882a593Smuzhiyun status = "okay"; 49*4882a593Smuzhiyun compatible = "galaxycore,gc2145"; 50*4882a593Smuzhiyun reg = <0x3c>; 51*4882a593Smuzhiyun //pinctrl-names = "default"; 52*4882a593Smuzhiyun //pinctrl-0 = <&cif_clkout_m0>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 55*4882a593Smuzhiyun clock-names = "xvclk"; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 58*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 59*4882a593Smuzhiyun dvdd-supply = <&vcc1v8_dvp>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; 62*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 63*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 64*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 65*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan"; 66*4882a593Smuzhiyun port { 67*4882a593Smuzhiyun gc2145_out: endpoint { 68*4882a593Smuzhiyun remote-endpoint = <&dvp_in_bcam>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&isp_mmu { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&rkisp1 { 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun pinctrl-names = "default"; 81*4882a593Smuzhiyun pinctrl-0 = <&dvp_d0d1_m0 &dvp_d2d9_m0>; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun ports { 84*4882a593Smuzhiyun #address-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <0>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun port@0 { 88*4882a593Smuzhiyun reg = <0>; 89*4882a593Smuzhiyun #address-cells = <1>; 90*4882a593Smuzhiyun #size-cells = <0>; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun dvp_in_fcam: endpoint@0 { 93*4882a593Smuzhiyun reg = <0>; 94*4882a593Smuzhiyun remote-endpoint = <&gc0312_out>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun dvp_in_bcam: endpoint@1 { 98*4882a593Smuzhiyun reg = <1>; 99*4882a593Smuzhiyun remote-endpoint = <&gc2145_out>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun}; 104