xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/rk3308b-mipi-display-v11.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
7*4882a593Smuzhiyun#include <dt-bindings/clock/rk618-cru.h>
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	backlight: backlight {
11*4882a593Smuzhiyun		status = "okay";
12*4882a593Smuzhiyun		compatible = "pwm-backlight";
13*4882a593Smuzhiyun		pwms = <&pwm1 0 25000 0>;
14*4882a593Smuzhiyun		brightness-levels = <
15*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
16*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
17*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
18*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
19*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
20*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
21*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
22*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
23*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
24*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
25*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
26*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
27*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
28*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
29*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
30*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
31*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
32*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
33*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
34*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
35*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
36*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
37*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
38*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
39*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
40*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
41*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
42*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
43*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
44*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
45*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
46*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
47*4882a593Smuzhiyun		default-brightness-level = <200>;
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	vcc3v3_lcd_n: vcc3v3-lcd-n {
51*4882a593Smuzhiyun		compatible = "regulator-fixed";
52*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd_n";
53*4882a593Smuzhiyun		pinctrl-names = "default";
54*4882a593Smuzhiyun		pinctrl-0 = <&lcd_en>;
55*4882a593Smuzhiyun		gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
56*4882a593Smuzhiyun		enable-active-high;
57*4882a593Smuzhiyun		regulator-boot-on;
58*4882a593Smuzhiyun	};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	reserved-memory {
61*4882a593Smuzhiyun		#address-cells = <2>;
62*4882a593Smuzhiyun		#size-cells = <2>;
63*4882a593Smuzhiyun		ranges;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		cma {
66*4882a593Smuzhiyun			compatible = "shared-dma-pool";
67*4882a593Smuzhiyun			reusable;
68*4882a593Smuzhiyun			size = <0x0 0x2000000>;
69*4882a593Smuzhiyun			linux,cma-default;
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&i2c0 {
75*4882a593Smuzhiyun	clock-frequency = <100000>;
76*4882a593Smuzhiyun	status = "okay";
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun	gt1x: gt1x@14 {
79*4882a593Smuzhiyun		compatible = "goodix,gt1x";
80*4882a593Smuzhiyun		reg = <0x14>;
81*4882a593Smuzhiyun		pinctrl-names = "default";
82*4882a593Smuzhiyun		pinctrl-0 = <&tp_int>;
83*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_n>;
84*4882a593Smuzhiyun		goodix,rst-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
85*4882a593Smuzhiyun		goodix,irq-gpio = <&gpio0 RK_PC0 IRQ_TYPE_LEVEL_LOW>;
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	rk618@50 {
89*4882a593Smuzhiyun		compatible = "rockchip,rk618";
90*4882a593Smuzhiyun		reg = <0x50>;
91*4882a593Smuzhiyun		pinctrl-names = "default";
92*4882a593Smuzhiyun		pinctrl-0 = <&i2s_8ch_0_mclk>;
93*4882a593Smuzhiyun		clocks = <&cru SCLK_I2S0_8CH_TX_OUT>;
94*4882a593Smuzhiyun		clock-names = "clkin";
95*4882a593Smuzhiyun		assigned-clocks = <&cru SCLK_I2S0_8CH_TX_OUT>;
96*4882a593Smuzhiyun		assigned-clock-rates = <12000000>;
97*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_n>;
98*4882a593Smuzhiyun		reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
99*4882a593Smuzhiyun		status = "okay";
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun		clock: cru {
102*4882a593Smuzhiyun			compatible = "rockchip,rk618-cru";
103*4882a593Smuzhiyun			clocks = <&cru SCLK_I2S0_8CH_TX_OUT>, <&cru DCLK_VOP>;
104*4882a593Smuzhiyun			clock-names = "clkin", "lcdc0_dclkp";
105*4882a593Smuzhiyun			assigned-clocks = <&clock SCALER_PLLIN_CLK>,
106*4882a593Smuzhiyun					  <&clock VIF_PLLIN_CLK>,
107*4882a593Smuzhiyun					  <&clock SCALER_CLK>,
108*4882a593Smuzhiyun					  <&clock VIF0_PRE_CLK>,
109*4882a593Smuzhiyun					  <&clock CODEC_CLK>,
110*4882a593Smuzhiyun					  <&clock DITHER_CLK>;
111*4882a593Smuzhiyun			assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_OUT>,
112*4882a593Smuzhiyun						 <&clock LCDC0_CLK>,
113*4882a593Smuzhiyun						 <&clock SCALER_PLL_CLK>,
114*4882a593Smuzhiyun						 <&clock VIF_PLL_CLK>,
115*4882a593Smuzhiyun						 <&cru SCLK_I2S0_8CH_TX_OUT>,
116*4882a593Smuzhiyun						 <&clock VIF0_CLK>;
117*4882a593Smuzhiyun			#clock-cells = <1>;
118*4882a593Smuzhiyun			status = "okay";
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		dsi {
122*4882a593Smuzhiyun			compatible = "rockchip,rk618-dsi";
123*4882a593Smuzhiyun			clocks = <&clock MIPI_CLK>;
124*4882a593Smuzhiyun			clock-names = "dsi";
125*4882a593Smuzhiyun			#address-cells = <1>;
126*4882a593Smuzhiyun			#size-cells = <0>;
127*4882a593Smuzhiyun			status = "okay";
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun			ports {
130*4882a593Smuzhiyun				#address-cells = <1>;
131*4882a593Smuzhiyun				#size-cells = <0>;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun				port@0 {
134*4882a593Smuzhiyun					reg = <0>;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun					dsi_in_rgb: endpoint {
137*4882a593Smuzhiyun						remote-endpoint = <&rgb_out_dsi>;
138*4882a593Smuzhiyun					};
139*4882a593Smuzhiyun				};
140*4882a593Smuzhiyun			};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun			panel@0 {
143*4882a593Smuzhiyun				compatible = "sitronix,st7703", "simple-panel-dsi";
144*4882a593Smuzhiyun				reg = <0>;
145*4882a593Smuzhiyun				power-supply = <&vcc3v3_lcd_n>;
146*4882a593Smuzhiyun				backlight = <&backlight>;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun				prepare-delay-ms = <0>;
149*4882a593Smuzhiyun				reset-delay-ms = <0>;
150*4882a593Smuzhiyun				init-delay-ms = <80>;
151*4882a593Smuzhiyun				enable-delay-ms = <0>;
152*4882a593Smuzhiyun				disable-delay-ms = <10>;
153*4882a593Smuzhiyun				unprepare-delay-ms = <60>;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun				width-mm = <68>;
156*4882a593Smuzhiyun				height-mm = <121>;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun				dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
159*4882a593Smuzhiyun					      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
160*4882a593Smuzhiyun				dsi,format = <MIPI_DSI_FMT_RGB888>;
161*4882a593Smuzhiyun				dsi,lanes = <4>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun				panel-init-sequence = [
164*4882a593Smuzhiyun					39 00 04 ff 98 81 03
165*4882a593Smuzhiyun					15 00 02 01 00
166*4882a593Smuzhiyun					15 00 02 02 00
167*4882a593Smuzhiyun					15 00 02 03 53
168*4882a593Smuzhiyun					15 00 02 04 53
169*4882a593Smuzhiyun					15 00 02 05 13
170*4882a593Smuzhiyun					15 00 02 06 04
171*4882a593Smuzhiyun					15 00 02 07 02
172*4882a593Smuzhiyun					15 00 02 08 02
173*4882a593Smuzhiyun					15 00 02 09 00
174*4882a593Smuzhiyun					15 00 02 0a 00
175*4882a593Smuzhiyun					15 00 02 0b 00
176*4882a593Smuzhiyun					15 00 02 0c 00
177*4882a593Smuzhiyun					15 00 02 0d 00
178*4882a593Smuzhiyun					15 00 02 0e 00
179*4882a593Smuzhiyun					15 00 02 0f 00
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun					15 00 02 10 00
182*4882a593Smuzhiyun					15 00 02 11 00
183*4882a593Smuzhiyun					15 00 02 12 00
184*4882a593Smuzhiyun					15 00 02 13 00
185*4882a593Smuzhiyun					15 00 02 14 00
186*4882a593Smuzhiyun					15 00 02 15 08
187*4882a593Smuzhiyun					15 00 02 16 10
188*4882a593Smuzhiyun					15 00 02 17 00
189*4882a593Smuzhiyun					15 00 02 18 08
190*4882a593Smuzhiyun					15 00 02 19 00
191*4882a593Smuzhiyun					15 00 02 1a 00
192*4882a593Smuzhiyun					15 00 02 1b 00
193*4882a593Smuzhiyun					15 00 02 1c 00
194*4882a593Smuzhiyun					15 00 02 1d 00
195*4882a593Smuzhiyun					15 00 02 1e c0
196*4882a593Smuzhiyun					15 00 02 1f 80
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun					15 00 02 20 02
199*4882a593Smuzhiyun					15 00 02 21 09
200*4882a593Smuzhiyun					15 00 02 22 00
201*4882a593Smuzhiyun					15 00 02 23 00
202*4882a593Smuzhiyun					15 00 02 24 00
203*4882a593Smuzhiyun					15 00 02 25 00
204*4882a593Smuzhiyun					15 00 02 26 00
205*4882a593Smuzhiyun					15 00 02 27 00
206*4882a593Smuzhiyun					15 00 02 28 55
207*4882a593Smuzhiyun					15 00 02 29 03
208*4882a593Smuzhiyun					15 00 02 2a 00
209*4882a593Smuzhiyun					15 00 02 2b 00
210*4882a593Smuzhiyun					15 00 02 2c 00
211*4882a593Smuzhiyun					15 00 02 2d 00
212*4882a593Smuzhiyun					15 00 02 2e 00
213*4882a593Smuzhiyun					15 00 02 2f 00
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun					15 00 02 30 00
216*4882a593Smuzhiyun					15 00 02 31 00
217*4882a593Smuzhiyun					15 00 02 32 00
218*4882a593Smuzhiyun					15 00 02 33 00
219*4882a593Smuzhiyun					15 00 02 34 04
220*4882a593Smuzhiyun					15 00 02 35 05
221*4882a593Smuzhiyun					15 00 02 36 05
222*4882a593Smuzhiyun					15 00 02 37 00
223*4882a593Smuzhiyun					15 00 02 38 3c
224*4882a593Smuzhiyun					15 00 02 39 35
225*4882a593Smuzhiyun					15 00 02 3a 00
226*4882a593Smuzhiyun					15 00 02 3b 40
227*4882a593Smuzhiyun					15 00 02 3c 00
228*4882a593Smuzhiyun					15 00 02 3d 00
229*4882a593Smuzhiyun					15 00 02 3e 00
230*4882a593Smuzhiyun					15 00 02 3f 00
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun					15 00 02 40 00
233*4882a593Smuzhiyun					15 00 02 41 88
234*4882a593Smuzhiyun					15 00 02 42 00
235*4882a593Smuzhiyun					15 00 02 43 00
236*4882a593Smuzhiyun					15 00 02 44 1f
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun					15 00 02 50 01
239*4882a593Smuzhiyun					15 00 02 51 23
240*4882a593Smuzhiyun					15 00 02 52 45
241*4882a593Smuzhiyun					15 00 02 53 67
242*4882a593Smuzhiyun					15 00 02 54 89
243*4882a593Smuzhiyun					15 00 02 55 ab
244*4882a593Smuzhiyun					15 00 02 56 01
245*4882a593Smuzhiyun					15 00 02 57 23
246*4882a593Smuzhiyun					15 00 02 58 45
247*4882a593Smuzhiyun					15 00 02 59 67
248*4882a593Smuzhiyun					15 00 02 5a 89
249*4882a593Smuzhiyun					15 00 02 5b ab
250*4882a593Smuzhiyun					15 00 02 5c cd
251*4882a593Smuzhiyun					15 00 02 5d ef
252*4882a593Smuzhiyun					15 00 02 5e 03
253*4882a593Smuzhiyun					15 00 02 5f 14
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun					15 00 02 60 15
256*4882a593Smuzhiyun					15 00 02 61 0c
257*4882a593Smuzhiyun					15 00 02 62 0d
258*4882a593Smuzhiyun					15 00 02 63 0e
259*4882a593Smuzhiyun					15 00 02 64 0f
260*4882a593Smuzhiyun					15 00 02 65 10
261*4882a593Smuzhiyun					15 00 02 66 11
262*4882a593Smuzhiyun					15 00 02 67 08
263*4882a593Smuzhiyun					15 00 02 68 02
264*4882a593Smuzhiyun					15 00 02 69 0a
265*4882a593Smuzhiyun					15 00 02 6a 02
266*4882a593Smuzhiyun					15 00 02 6b 02
267*4882a593Smuzhiyun					15 00 02 6c 02
268*4882a593Smuzhiyun					15 00 02 6d 02
269*4882a593Smuzhiyun					15 00 02 6e 02
270*4882a593Smuzhiyun					15 00 02 6f 02
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun					15 00 02 70 02
273*4882a593Smuzhiyun					15 00 02 71 02
274*4882a593Smuzhiyun					15 00 02 72 06
275*4882a593Smuzhiyun					15 00 02 73 02
276*4882a593Smuzhiyun					15 00 02 74 02
277*4882a593Smuzhiyun					15 00 02 75 14
278*4882a593Smuzhiyun					15 00 02 76 15
279*4882a593Smuzhiyun					15 00 02 77 0f
280*4882a593Smuzhiyun					15 00 02 78 0e
281*4882a593Smuzhiyun					15 00 02 79 0d
282*4882a593Smuzhiyun					15 00 02 7a 0c
283*4882a593Smuzhiyun					15 00 02 7b 11
284*4882a593Smuzhiyun					15 00 02 7c 10
285*4882a593Smuzhiyun					15 00 02 7d 06
286*4882a593Smuzhiyun					15 00 02 7e 02
287*4882a593Smuzhiyun					15 00 02 7f 0a
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun					15 00 02 80 02
290*4882a593Smuzhiyun					15 00 02 81 02
291*4882a593Smuzhiyun					15 00 02 82 02
292*4882a593Smuzhiyun					15 00 02 83 02
293*4882a593Smuzhiyun					15 00 02 84 02
294*4882a593Smuzhiyun					15 00 02 85 02
295*4882a593Smuzhiyun					15 00 02 86 02
296*4882a593Smuzhiyun					15 00 02 87 02
297*4882a593Smuzhiyun					15 00 02 88 08
298*4882a593Smuzhiyun					15 00 02 89 02
299*4882a593Smuzhiyun					15 00 02 8a 02
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun					39 00 04 ff 98 81 04
302*4882a593Smuzhiyun					15 00 02 00 80
303*4882a593Smuzhiyun					15 00 02 70 00
304*4882a593Smuzhiyun					15 00 02 71 00
305*4882a593Smuzhiyun					15 00 02 66 fe
306*4882a593Smuzhiyun					15 00 02 82 15
307*4882a593Smuzhiyun					15 00 02 84 15
308*4882a593Smuzhiyun					15 00 02 85 15
309*4882a593Smuzhiyun					15 00 02 3a 24
310*4882a593Smuzhiyun					15 00 02 32 ac
311*4882a593Smuzhiyun					15 00 02 8c 80
312*4882a593Smuzhiyun					15 00 02 3c f5
313*4882a593Smuzhiyun					15 00 02 88 33
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun					39 00 04 ff 98 81 01
316*4882a593Smuzhiyun					15 00 02 22 0a
317*4882a593Smuzhiyun					15 00 02 31 00
318*4882a593Smuzhiyun					15 00 02 53 78
319*4882a593Smuzhiyun					15 00 02 50 5b
320*4882a593Smuzhiyun					15 00 02 51 5b
321*4882a593Smuzhiyun					15 00 02 60 20
322*4882a593Smuzhiyun					15 00 02 61 00
323*4882a593Smuzhiyun					15 00 02 62 0d
324*4882a593Smuzhiyun					15 00 02 63 00
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun					15 00 02 a0 00
327*4882a593Smuzhiyun					15 00 02 a1 10
328*4882a593Smuzhiyun					15 00 02 a2 1c
329*4882a593Smuzhiyun					15 00 02 a3 13
330*4882a593Smuzhiyun					15 00 02 a4 15
331*4882a593Smuzhiyun					15 00 02 a5 26
332*4882a593Smuzhiyun					15 00 02 a6 1a
333*4882a593Smuzhiyun					15 00 02 a7 1d
334*4882a593Smuzhiyun					15 00 02 a8 67
335*4882a593Smuzhiyun					15 00 02 a9 1c
336*4882a593Smuzhiyun					15 00 02 aa 29
337*4882a593Smuzhiyun					15 00 02 ab 5b
338*4882a593Smuzhiyun					15 00 02 ac 26
339*4882a593Smuzhiyun					15 00 02 ad 28
340*4882a593Smuzhiyun					15 00 02 ae 5c
341*4882a593Smuzhiyun					15 00 02 af 30
342*4882a593Smuzhiyun					15 00 02 b0 31
343*4882a593Smuzhiyun					15 00 02 b1 2e
344*4882a593Smuzhiyun					15 00 02 b2 32
345*4882a593Smuzhiyun					15 00 02 b3 00
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun					15 00 02 c0 00
348*4882a593Smuzhiyun					15 00 02 c1 10
349*4882a593Smuzhiyun					15 00 02 c2 1c
350*4882a593Smuzhiyun					15 00 02 c3 13
351*4882a593Smuzhiyun					15 00 02 c4 15
352*4882a593Smuzhiyun					15 00 02 c5 26
353*4882a593Smuzhiyun					15 00 02 c6 1a
354*4882a593Smuzhiyun					15 00 02 c7 1d
355*4882a593Smuzhiyun					15 00 02 c8 67
356*4882a593Smuzhiyun					15 00 02 c9 1c
357*4882a593Smuzhiyun					15 00 02 ca 29
358*4882a593Smuzhiyun					15 00 02 cb 5b
359*4882a593Smuzhiyun					15 00 02 cc 26
360*4882a593Smuzhiyun					15 00 02 cd 28
361*4882a593Smuzhiyun					15 00 02 ce 5c
362*4882a593Smuzhiyun					15 00 02 cf 30
363*4882a593Smuzhiyun					15 00 02 d0 31
364*4882a593Smuzhiyun					15 00 02 d1 2e
365*4882a593Smuzhiyun					15 00 02 d2 32
366*4882a593Smuzhiyun					15 00 02 d3 00
367*4882a593Smuzhiyun					39 00 04 ff 98 81 00
368*4882a593Smuzhiyun					05 00 01 11
369*4882a593Smuzhiyun					05 01 01 29
370*4882a593Smuzhiyun				];
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun				panel-exit-sequence = [
373*4882a593Smuzhiyun					05 00 01 28
374*4882a593Smuzhiyun					05 00 01 10
375*4882a593Smuzhiyun				];
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun				display-timings {
378*4882a593Smuzhiyun					native-mode = <&timing0>;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun					timing0: timing0 {
381*4882a593Smuzhiyun						clock-frequency = <65000000>;
382*4882a593Smuzhiyun						hactive = <720>;
383*4882a593Smuzhiyun						vactive = <1280>;
384*4882a593Smuzhiyun						hfront-porch = <48>;
385*4882a593Smuzhiyun						hsync-len = <8>;
386*4882a593Smuzhiyun						hback-porch = <52>;
387*4882a593Smuzhiyun						vfront-porch = <16>;
388*4882a593Smuzhiyun						vsync-len = <6>;
389*4882a593Smuzhiyun						vback-porch = <15>;
390*4882a593Smuzhiyun						hsync-active = <0>;
391*4882a593Smuzhiyun						vsync-active = <0>;
392*4882a593Smuzhiyun						de-active = <0>;
393*4882a593Smuzhiyun						pixelclk-active = <0>;
394*4882a593Smuzhiyun					};
395*4882a593Smuzhiyun				};
396*4882a593Smuzhiyun			};
397*4882a593Smuzhiyun		};
398*4882a593Smuzhiyun	};
399*4882a593Smuzhiyun};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun&display_subsystem {
403*4882a593Smuzhiyun	status = "okay";
404*4882a593Smuzhiyun};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun&pinctrl {
407*4882a593Smuzhiyun	lcd {
408*4882a593Smuzhiyun		lcd_en: lcd-en {
409*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
410*4882a593Smuzhiyun		};
411*4882a593Smuzhiyun		tp_int: tp-int {
412*4882a593Smuzhiyun			rockchip,pins =	<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
413*4882a593Smuzhiyun		};
414*4882a593Smuzhiyun	};
415*4882a593Smuzhiyun};
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun&pwm1 {
418*4882a593Smuzhiyun	status = "okay";
419*4882a593Smuzhiyun};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun&rgb {
422*4882a593Smuzhiyun	status = "okay";
423*4882a593Smuzhiyun	pinctrl-names = "default";
424*4882a593Smuzhiyun	pinctrl-0 = <&lcdc_ctl &lcdc_rgb888_m1>;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun	ports {
427*4882a593Smuzhiyun		rgb_out: port@1 {
428*4882a593Smuzhiyun			reg = <1>;
429*4882a593Smuzhiyun			#address-cells = <1>;
430*4882a593Smuzhiyun			#size-cells = <0>;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun			rgb_out_dsi: endpoint@0 {
433*4882a593Smuzhiyun				reg = <0>;
434*4882a593Smuzhiyun				remote-endpoint = <&dsi_in_rgb>;
435*4882a593Smuzhiyun			};
436*4882a593Smuzhiyun		};
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun&route_rgb {
441*4882a593Smuzhiyun	logo,kernel = "logo_kernel.bmp";
442*4882a593Smuzhiyun	status = "okay";
443*4882a593Smuzhiyun};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun&vop {
446*4882a593Smuzhiyun	status = "okay";
447*4882a593Smuzhiyun};
448