1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun rockchip_amp: rockchip-amp { 8*4882a593Smuzhiyun compatible = "rockchip,amp"; 9*4882a593Smuzhiyun clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>, 10*4882a593Smuzhiyun <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>, <&cru SCLK_TIMER5>; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun pinctrl-names = "default"; 13*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer>; 14*4882a593Smuzhiyun status = "okay"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun reserved-memory { 18*4882a593Smuzhiyun #address-cells = <2>; 19*4882a593Smuzhiyun #size-cells = <2>; 20*4882a593Smuzhiyun ranges; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* remote amp core address */ 23*4882a593Smuzhiyun amp_reserved: amp@2e00000 { 24*4882a593Smuzhiyun reg = <0x0 0x2e00000 0x0 0x1200000>; 25*4882a593Smuzhiyun no-map; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&cpu3 { 31*4882a593Smuzhiyun status = "disabled"; 32*4882a593Smuzhiyun}; 33