1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3308.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Rockchip RK3308 FPGA Platform"; 13*4882a593Smuzhiyun compatible = "rockchip,rk3308-fpga", "rockchip,rk3308"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff0b0000 console=ttyFIQ0 init=/init initrd=0x9000000,0x18bfc0"; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun memory@200000 { 20*4882a593Smuzhiyun device_type = "memory"; 21*4882a593Smuzhiyun reg = <0x0 0x00200000 0x0 0x0FE00000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&fiq_debugger { 26*4882a593Smuzhiyun rockchip,serial-id = <1>; 27*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 28*4882a593Smuzhiyun status = "ok"; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&cpu1 { 32*4882a593Smuzhiyun /delete-property/enable-method; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun&cpu2 { 36*4882a593Smuzhiyun /delete-property/enable-method; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&cpu3 { 40*4882a593Smuzhiyun /delete-property/enable-method; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&emmc { 44*4882a593Smuzhiyun cap-mmc-highspeed; 45*4882a593Smuzhiyun mmc-hs200-1_8v; 46*4882a593Smuzhiyun no-sdio; 47*4882a593Smuzhiyun no-sd; 48*4882a593Smuzhiyun non-removable; 49*4882a593Smuzhiyun num-slots = <1>; 50*4882a593Smuzhiyun status = "okay"; 51*4882a593Smuzhiyun}; 52