1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun backlight: backlight { 9*4882a593Smuzhiyun status = "okay"; 10*4882a593Smuzhiyun compatible = "pwm-backlight"; 11*4882a593Smuzhiyun pwms = <&pwm1 0 25000 0>; 12*4882a593Smuzhiyun brightness-levels = < 13*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 14*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 15*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 16*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 17*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 18*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 19*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 20*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 21*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 22*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 23*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 24*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 25*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 26*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 27*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 28*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 29*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 30*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 31*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 32*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 33*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 34*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 35*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 36*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 37*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 38*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 39*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 40*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 41*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 42*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 43*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 44*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 45*4882a593Smuzhiyun default-brightness-level = <200>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun panel: panel { 49*4882a593Smuzhiyun compatible = "simple-panel"; 50*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB666_1X18>; 51*4882a593Smuzhiyun backlight = <&backlight>; 52*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; 53*4882a593Smuzhiyun enable-delay-ms = <20>; 54*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; 55*4882a593Smuzhiyun reset-delay-ms = <10>; 56*4882a593Smuzhiyun prepare-delay-ms = <20>; 57*4882a593Smuzhiyun unprepare-delay-ms = <20>; 58*4882a593Smuzhiyun disable-delay-ms = <20>; 59*4882a593Smuzhiyun /* spi-sdo-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; */ 60*4882a593Smuzhiyun spi-sdi-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; 61*4882a593Smuzhiyun spi-scl-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; 62*4882a593Smuzhiyun spi-cs-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; 63*4882a593Smuzhiyun width-mm = <217>; 64*4882a593Smuzhiyun height-mm = <136>; 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun pinctrl-names = "default"; 67*4882a593Smuzhiyun pinctrl-0 = <&spi_init_cmd>; 68*4882a593Smuzhiyun rockchip,cmd-type = "spi"; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* type:0 is cmd, 1 is data */ 71*4882a593Smuzhiyun panel-init-sequence = [ 72*4882a593Smuzhiyun /* type delay num val1 val2 val3 */ 73*4882a593Smuzhiyun 00 00 01 e0 74*4882a593Smuzhiyun 01 00 01 00 75*4882a593Smuzhiyun 01 00 01 07 76*4882a593Smuzhiyun 01 00 01 0f 77*4882a593Smuzhiyun 01 00 01 0d 78*4882a593Smuzhiyun 01 00 01 1b 79*4882a593Smuzhiyun 01 00 01 0a 80*4882a593Smuzhiyun 01 00 01 3c 81*4882a593Smuzhiyun 01 00 01 78 82*4882a593Smuzhiyun 01 00 01 4a 83*4882a593Smuzhiyun 01 00 01 07 84*4882a593Smuzhiyun 01 00 01 0e 85*4882a593Smuzhiyun 01 00 01 09 86*4882a593Smuzhiyun 01 00 01 1b 87*4882a593Smuzhiyun 01 00 01 1e 88*4882a593Smuzhiyun 01 00 01 0f 89*4882a593Smuzhiyun 00 00 01 e1 90*4882a593Smuzhiyun 01 00 01 00 91*4882a593Smuzhiyun 01 00 01 22 92*4882a593Smuzhiyun 01 00 01 24 93*4882a593Smuzhiyun 01 00 01 06 94*4882a593Smuzhiyun 01 00 01 12 95*4882a593Smuzhiyun 01 00 01 07 96*4882a593Smuzhiyun 01 00 01 36 97*4882a593Smuzhiyun 01 00 01 47 98*4882a593Smuzhiyun 01 00 01 47 99*4882a593Smuzhiyun 01 00 01 06 100*4882a593Smuzhiyun 01 00 01 0a 101*4882a593Smuzhiyun 01 00 01 07 102*4882a593Smuzhiyun 01 00 01 30 103*4882a593Smuzhiyun 01 00 01 37 104*4882a593Smuzhiyun 01 00 01 0f 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun 00 00 01 c0 107*4882a593Smuzhiyun 01 00 01 10 108*4882a593Smuzhiyun 01 00 01 10 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun 00 00 01 c1 111*4882a593Smuzhiyun 01 00 01 41 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun 00 00 01 c5 114*4882a593Smuzhiyun 01 00 01 00 115*4882a593Smuzhiyun 01 00 01 22 116*4882a593Smuzhiyun 01 00 01 80 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun 00 00 01 36 119*4882a593Smuzhiyun 01 00 01 48 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun 00 00 01 3a //interface pixel format 122*4882a593Smuzhiyun 01 00 01 66 // bpp cfg 123*4882a593Smuzhiyun // 3 11 124*4882a593Smuzhiyun // 16 55 125*4882a593Smuzhiyun // 18 66 126*4882a593Smuzhiyun // 24 77 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun 00 00 01 b0 /* interface mode control */ 129*4882a593Smuzhiyun 01 00 01 00 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun 00 00 01 b1 /* frame rate 60hz */ 132*4882a593Smuzhiyun 01 00 01 a0 133*4882a593Smuzhiyun 01 00 01 11 134*4882a593Smuzhiyun 00 00 01 b4 135*4882a593Smuzhiyun 01 00 01 02 136*4882a593Smuzhiyun 00 00 01 B6 137*4882a593Smuzhiyun 01 00 01 32 138*4882a593Smuzhiyun 01 00 01 02 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun 00 00 01 b7 141*4882a593Smuzhiyun 01 00 01 c6 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun 00 00 01 be 144*4882a593Smuzhiyun 01 00 01 00 145*4882a593Smuzhiyun 01 00 01 04 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun 00 00 01 e9 148*4882a593Smuzhiyun 01 00 01 00 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun 00 00 01 f7 151*4882a593Smuzhiyun 01 00 01 a9 152*4882a593Smuzhiyun 01 00 01 51 153*4882a593Smuzhiyun 01 00 01 2c 154*4882a593Smuzhiyun 01 00 01 82 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun 00 78 01 11 157*4882a593Smuzhiyun 00 00 01 29 158*4882a593Smuzhiyun ]; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun panel-exit-sequence = [ 161*4882a593Smuzhiyun /* type delay num val1 val2 val3 */ 162*4882a593Smuzhiyun 00 0a 01 28 163*4882a593Smuzhiyun 00 78 01 10 164*4882a593Smuzhiyun ]; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun display-timings { 167*4882a593Smuzhiyun native-mode = <&kd050fwfba002_timing>; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun kd050fwfba002_timing: timing0 { 170*4882a593Smuzhiyun clock-frequency = <94081500>; 171*4882a593Smuzhiyun hactive = <320>; 172*4882a593Smuzhiyun vactive = <480>; 173*4882a593Smuzhiyun hback-porch = <10>; 174*4882a593Smuzhiyun hfront-porch = <5>; 175*4882a593Smuzhiyun vback-porch = <10>; 176*4882a593Smuzhiyun vfront-porch = <5>; 177*4882a593Smuzhiyun hsync-len = <10>; 178*4882a593Smuzhiyun vsync-len = <10>; 179*4882a593Smuzhiyun hsync-active = <0>; 180*4882a593Smuzhiyun vsync-active = <0>; 181*4882a593Smuzhiyun de-active = <0>; 182*4882a593Smuzhiyun pixelclk-active = <0>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun port { 187*4882a593Smuzhiyun panel_in_rgb: endpoint { 188*4882a593Smuzhiyun remote-endpoint = <&rgb_out_panel>; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun&display_subsystem { 195*4882a593Smuzhiyun status = "okay"; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&pinctrl { 199*4882a593Smuzhiyun spi_panel { 200*4882a593Smuzhiyun spi_init_cmd: spi-init-cmd { 201*4882a593Smuzhiyun rockchip,pins = 202*4882a593Smuzhiyun /* spi sdi */ 203*4882a593Smuzhiyun <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, 204*4882a593Smuzhiyun /* spi scl */ 205*4882a593Smuzhiyun <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 206*4882a593Smuzhiyun /* spi cs */ 207*4882a593Smuzhiyun <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&pwm1 { 213*4882a593Smuzhiyun status = "okay"; 214*4882a593Smuzhiyun}; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun&rgb { 217*4882a593Smuzhiyun status = "okay"; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun ports { 220*4882a593Smuzhiyun rgb_out: port@1 { 221*4882a593Smuzhiyun reg = <1>; 222*4882a593Smuzhiyun #address-cells = <1>; 223*4882a593Smuzhiyun #size-cells = <0>; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun rgb_out_panel: endpoint@0 { 226*4882a593Smuzhiyun reg = <0>; 227*4882a593Smuzhiyun remote-endpoint = <&panel_in_rgb>; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&route_rgb { 234*4882a593Smuzhiyun status = "okay"; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&vop { 238*4882a593Smuzhiyun status = "okay"; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun mcu-timing { 241*4882a593Smuzhiyun mcu-pix-total = <9>; 242*4882a593Smuzhiyun mcu-cs-pst = <1>; 243*4882a593Smuzhiyun mcu-cs-pend = <8>; 244*4882a593Smuzhiyun mcu-rw-pst = <2>; 245*4882a593Smuzhiyun mcu-rw-pend = <5>; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun mcu-hold-mode = <0>; // default set to 0 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun}; 250