1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6/dts-v1/; 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/display/drm_mipi_dsi.h> 11#include <dt-bindings/display/media-bus-format.h> 12#include <dt-bindings/clock/rk618-cru.h> 13#include "px30.dtsi" 14#include "px30-android.dtsi" 15 16/ { 17 model = "Rockchip PX30 Z7 A0 board"; 18 compatible = "rockchip,px30-z7-a0", "rockchip,px30"; 19 20 adc-keys { 21 compatible = "adc-keys"; 22 io-channels = <&saradc 2>; 23 io-channel-names = "buttons"; 24 poll-interval = <100>; 25 keyup-threshold-microvolt = <1800000>; 26 27 esc-key { 28 linux,code = <KEY_ESC>; 29 label = "esc"; 30 press-threshold-microvolt = <1310000>; 31 }; 32 33 home-key { 34 linux,code = <KEY_HOME>; 35 label = "home"; 36 press-threshold-microvolt = <624000>; 37 }; 38 39 menu-key { 40 linux,code = <KEY_MENU>; 41 label = "menu"; 42 press-threshold-microvolt = <987000>; 43 }; 44 45 vol-down-key { 46 linux,code = <KEY_VOLUMEDOWN>; 47 label = "volume down"; 48 press-threshold-microvolt = <300000>; 49 }; 50 51 vol-up-key { 52 linux,code = <KEY_VOLUMEUP>; 53 label = "volume up"; 54 press-threshold-microvolt = <17000>; 55 }; 56 }; 57 58 backlight: backlight { 59 compatible = "pwm-backlight"; 60 pwms = <&pwm0 0 25000 0>; 61 brightness-levels = < 62 0 1 2 3 4 5 6 7 63 8 9 10 11 12 13 14 15 64 16 17 18 19 20 21 22 23 65 24 25 26 27 28 29 30 31 66 32 33 34 35 36 37 38 39 67 40 41 42 43 44 45 46 47 68 48 49 50 51 52 53 54 55 69 56 57 58 59 60 61 62 63 70 64 65 66 67 68 69 70 71 71 72 73 74 75 76 77 78 79 72 80 81 82 83 84 85 86 87 73 88 89 90 91 92 93 94 95 74 96 97 98 99 100 101 102 103 75 104 105 106 107 108 109 110 111 76 112 113 114 115 116 117 118 119 77 120 121 122 123 124 125 126 127 78 128 129 130 131 132 133 134 135 79 136 137 138 139 140 141 142 143 80 144 145 146 147 148 149 150 151 81 152 153 154 155 156 157 158 159 82 160 161 162 163 164 165 166 167 83 168 169 170 171 172 173 174 175 84 176 177 178 179 180 181 182 183 85 184 185 186 187 188 189 190 191 86 192 193 194 195 196 197 198 199 87 200 201 202 203 204 205 206 207 88 208 209 210 211 212 213 214 215 89 216 217 218 219 220 221 222 223 90 224 225 226 227 228 229 230 231 91 232 233 234 235 236 237 238 239 92 240 241 242 243 244 245 246 247 93 248 249 250 251 252 253 254 255>; 94 default-brightness-level = <200>; 95 }; 96 97 sdio_pwrseq: sdio-pwrseq { 98 compatible = "mmc-pwrseq-simple"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&wifi_enable_h>; 101 102 /* 103 * On the module itself this is one of these (depending 104 * on the actual card populated): 105 * - SDIO_RESET_L_WL_REG_ON 106 * - PDN (power down when low) 107 */ 108 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 109 }; 110 111 vcc_phy: vcc-phy-regulator { 112 compatible = "regulator-fixed"; 113 regulator-name = "vcc_phy"; 114 regulator-always-on; 115 regulator-boot-on; 116 }; 117 118 vcc5v0_sys: vccsys { 119 compatible = "regulator-fixed"; 120 regulator-name = "vcc5v0_sys"; 121 regulator-always-on; 122 regulator-boot-on; 123 regulator-min-microvolt = <5000000>; 124 regulator-max-microvolt = <5000000>; 125 }; 126}; 127 128&display_subsystem { 129 status = "okay"; 130}; 131 132&dsi { 133 status = "okay"; 134 135 panel@0 { 136 compatible = "simple-panel-dsi"; 137 reg = <0>; 138 power-supply = <&vcc3v3_lcd>; 139 backlight = <&backlight>; 140 reset-gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; 141 prepare-delay-ms = <20>; 142 reset-delay-ms = <20>; 143 init-delay-ms = <20>; 144 enable-delay-ms = <120>; 145 disable-delay-ms = <20>; 146 unprepare-delay-ms = <20>; 147 148 width-mm = <95>; 149 height-mm = <151>; 150 151 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 152 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 153 dsi,format = <MIPI_DSI_FMT_RGB888>; 154 dsi,lanes = <4>; 155 156 panel-init-sequence = [ 157 15 00 02 b0 00 158 15 00 02 d6 01 159 39 00 06 b3 14 08 00 22 00 160 15 00 02 b4 0c 161 15 00 02 de 00 162 39 00 03 b6 3a d3 163 15 00 02 51 e0 164 15 00 02 53 04 165 15 00 02 3a 77 166 15 00 02 35 01 167 39 00 05 2a 00 00 04 af 168 39 00 05 2b 00 00 07 7f 169 05 96 01 29 170 05 14 01 11 171 ]; 172 173 panel-exit-sequence = [ 174 05 00 01 28 175 05 00 01 10 176 ]; 177 178 display-timings { 179 native-mode = <&timing0>; 180 181 timing0: timing0 { 182 clock-frequency = <156000000>; 183 hactive = <1200>; 184 vactive = <1920>; 185 hback-porch = <60>; 186 hfront-porch = <80>; 187 vback-porch = <4>; 188 vfront-porch = <4>; 189 hsync-len = <10>; 190 vsync-len = <1>; 191 hsync-active = <0>; 192 vsync-active = <0>; 193 de-active = <0>; 194 pixelclk-active = <0>; 195 }; 196 }; 197 198 ports { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 202 port@0 { 203 reg = <0>; 204 panel_in_dsi: endpoint { 205 remote-endpoint = <&dsi_out_panel>; 206 }; 207 }; 208 }; 209 }; 210 211 ports { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 215 port@1 { 216 reg = <1>; 217 dsi_out_panel: endpoint { 218 remote-endpoint = <&panel_in_dsi>; 219 }; 220 }; 221 }; 222}; 223 224&dsi_in_vopb { 225 status = "okay"; 226}; 227 228&dsi_in_vopl { 229 status = "disabled"; 230}; 231 232&route_dsi { 233 connect = <&vopb_out_dsi>; 234 status = "okay"; 235}; 236 237&bus_apll { 238 bus-supply = <&vdd_logic>; 239 status = "okay"; 240}; 241 242&cpu0 { 243 cpu-supply = <&vdd_arm>; 244}; 245 246&dfi { 247 status = "okay"; 248}; 249 250&dmc { 251 center-supply = <&vdd_logic>; 252 auto-freq-en = <0>; 253 status = "okay"; 254}; 255 256&emmc { 257 bus-width = <8>; 258 cap-mmc-highspeed; 259 mmc-hs200-1_8v; 260 no-sdio; 261 no-sd; 262 disable-wp; 263 non-removable; 264 num-slots = <1>; 265 status = "okay"; 266}; 267 268&gpu { 269 mali-supply = <&vdd_logic>; 270 status = "okay"; 271}; 272 273&i2c0 { 274 status = "okay"; 275 276 rk809: pmic@20 { 277 compatible = "rockchip,rk809"; 278 reg = <0x20>; 279 interrupt-parent = <&gpio0>; 280 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 281 pinctrl-names = "default", "pmic-sleep", 282 "pmic-power-off", "pmic-reset"; 283 pinctrl-0 = <&pmic_int>; 284 pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 285 pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 286 pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 287 rockchip,system-power-controller; 288 wakeup-source; 289 #clock-cells = <1>; 290 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 291 pmic-reset-func = <1>; 292 293 vcc1-supply = <&vcc5v0_sys>; 294 vcc2-supply = <&vcc5v0_sys>; 295 vcc3-supply = <&vcc5v0_sys>; 296 vcc4-supply = <&vcc5v0_sys>; 297 vcc5-supply = <&vcc3v3_sys>; 298 vcc6-supply = <&vcc3v3_sys>; 299 vcc7-supply = <&vcc3v3_sys>; 300 vcc8-supply = <&vcc3v3_sys>; 301 vcc9-supply = <&vcc5v0_sys>; 302 303 pwrkey { 304 status = "okay"; 305 }; 306 307 pinctrl_rk8xx: pinctrl_rk8xx { 308 gpio-controller; 309 #gpio-cells = <2>; 310 311 rk817_slppin_null: rk817_slppin_null { 312 pins = "gpio_slp"; 313 function = "pin_fun0"; 314 }; 315 316 rk817_slppin_slp: rk817_slppin_slp { 317 pins = "gpio_slp"; 318 function = "pin_fun1"; 319 }; 320 321 rk817_slppin_pwrdn: rk817_slppin_pwrdn { 322 pins = "gpio_slp"; 323 function = "pin_fun2"; 324 }; 325 326 rk817_slppin_rst: rk817_slppin_rst { 327 pins = "gpio_slp"; 328 function = "pin_fun3"; 329 }; 330 }; 331 332 regulators { 333 vdd_logic: DCDC_REG1 { 334 regulator-always-on; 335 regulator-boot-on; 336 regulator-min-microvolt = <850000>; 337 regulator-max-microvolt = <1350000>; 338 regulator-ramp-delay = <6001>; 339 regulator-initial-mode = <0x2>; 340 regulator-name = "vdd_logic"; 341 342 regulator-state-mem { 343 regulator-on-in-suspend; 344 regulator-suspend-microvolt = <950000>; 345 }; 346 }; 347 348 vdd_arm: DCDC_REG2 { 349 regulator-always-on; 350 regulator-boot-on; 351 regulator-min-microvolt = <850000>; 352 regulator-max-microvolt = <1350000>; 353 regulator-ramp-delay = <6001>; 354 regulator-initial-mode = <0x2>; 355 regulator-name = "vdd_arm"; 356 357 regulator-state-mem { 358 regulator-off-in-suspend; 359 regulator-suspend-microvolt = <950000>; 360 }; 361 }; 362 363 vcc_ddr: DCDC_REG3 { 364 regulator-always-on; 365 regulator-boot-on; 366 regulator-name = "vcc_ddr"; 367 regulator-initial-mode = <0x2>; 368 369 regulator-state-mem { 370 regulator-on-in-suspend; 371 }; 372 }; 373 374 vcc_3v0: DCDC_REG4 { 375 regulator-always-on; 376 regulator-boot-on; 377 regulator-min-microvolt = <3000000>; 378 regulator-max-microvolt = <3000000>; 379 regulator-initial-mode = <0x2>; 380 regulator-name = "vcc_3v0"; 381 382 regulator-state-mem { 383 regulator-on-in-suspend; 384 regulator-suspend-microvolt = <3000000>; 385 }; 386 }; 387 388 vcc_1v0: LDO_REG1 { 389 regulator-always-on; 390 regulator-boot-on; 391 regulator-min-microvolt = <1000000>; 392 regulator-max-microvolt = <1000000>; 393 regulator-name = "vcc_1v0"; 394 395 regulator-state-mem { 396 regulator-on-in-suspend; 397 regulator-suspend-microvolt = <1000000>; 398 }; 399 }; 400 401 vcc1v8_soc: LDO_REG2 { 402 regulator-always-on; 403 regulator-boot-on; 404 regulator-min-microvolt = <1800000>; 405 regulator-max-microvolt = <1800000>; 406 regulator-name = "vcc1v8_soc"; 407 408 regulator-state-mem { 409 regulator-on-in-suspend; 410 regulator-suspend-microvolt = <1800000>; 411 }; 412 }; 413 414 vdd1v0_soc: LDO_REG3 { 415 regulator-always-on; 416 regulator-boot-on; 417 regulator-min-microvolt = <1000000>; 418 regulator-max-microvolt = <1000000>; 419 regulator-name = "vcc1v0_soc"; 420 421 regulator-state-mem { 422 regulator-on-in-suspend; 423 regulator-suspend-microvolt = <1000000>; 424 }; 425 }; 426 427 vcc3v0_pmu: LDO_REG4 { 428 regulator-always-on; 429 regulator-boot-on; 430 regulator-min-microvolt = <3300000>; 431 regulator-max-microvolt = <3300000>; 432 regulator-name = "vcc3v0_pmu"; 433 434 regulator-state-mem { 435 regulator-on-in-suspend; 436 regulator-suspend-microvolt = <3300000>; 437 }; 438 }; 439 440 vccio_sd: LDO_REG5 { 441 regulator-always-on; 442 regulator-boot-on; 443 regulator-min-microvolt = <1800000>; 444 regulator-max-microvolt = <3300000>; 445 regulator-name = "vccio_sd"; 446 447 regulator-state-mem { 448 regulator-on-in-suspend; 449 regulator-suspend-microvolt = <3300000>; 450 }; 451 }; 452 453 vcc_sd: LDO_REG6 { 454 regulator-min-microvolt = <3300000>; 455 regulator-max-microvolt = <3300000>; 456 regulator-name = "vcc_sd"; 457 458 regulator-state-mem { 459 regulator-on-in-suspend; 460 regulator-suspend-microvolt = <3300000>; 461 }; 462 }; 463 464 vcc2v8_dvp: LDO_REG7 { 465 regulator-always-on; 466 regulator-boot-on; 467 regulator-min-microvolt = <2800000>; 468 regulator-max-microvolt = <2800000>; 469 regulator-name = "vcc2v8_dvp"; 470 471 regulator-state-mem { 472 regulator-off-in-suspend; 473 regulator-suspend-microvolt = <2800000>; 474 }; 475 }; 476 477 vcc1v8_dvp: LDO_REG8 { 478 regulator-always-on; 479 regulator-boot-on; 480 regulator-min-microvolt = <1800000>; 481 regulator-max-microvolt = <1800000>; 482 regulator-name = "vcc1v8_dvp"; 483 484 regulator-state-mem { 485 regulator-on-in-suspend; 486 regulator-suspend-microvolt = <1800000>; 487 }; 488 }; 489 490 vdd1v5_dvp: LDO_REG9 { 491 regulator-always-on; 492 regulator-boot-on; 493 regulator-min-microvolt = <1500000>; 494 regulator-max-microvolt = <1500000>; 495 regulator-name = "vdd1v5_dvp"; 496 497 regulator-state-mem { 498 regulator-off-in-suspend; 499 regulator-suspend-microvolt = <1500000>; 500 }; 501 }; 502 503 vcc3v3_sys: DCDC_REG5 { 504 regulator-always-on; 505 regulator-boot-on; 506 regulator-min-microvolt = <3300000>; 507 regulator-max-microvolt = <3300000>; 508 regulator-name = "vcc3v3_sys"; 509 510 regulator-state-mem { 511 regulator-on-in-suspend; 512 regulator-suspend-microvolt = <3300000>; 513 }; 514 }; 515 516 vcc5v0_host: SWITCH_REG1 { 517 regulator-always-on; 518 regulator-boot-on; 519 regulator-name = "vcc5v0_host"; 520 }; 521 522 vcc3v3_lcd: SWITCH_REG2 { 523 regulator-boot-on; 524 regulator-name = "vcc3v3_lcd"; 525 }; 526 }; 527 }; 528 529 rk618@50 { 530 compatible = "rockchip,rk618"; 531 reg = <0x50>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&i2s1_2ch_mclk>; 534 clocks = <&cru SCLK_I2S1_OUT>; 535 clock-names = "clkin"; 536 assigned-clocks = <&cru SCLK_I2S1_OUT>; 537 assigned-clock-rates = <12000000>; 538 reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; 539 status = "okay"; 540 541 clock: cru { 542 compatible = "rockchip,rk618-cru"; 543 clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; 544 clock-names = "clkin", "lcdc0_dclkp"; 545 assigned-clocks = <&clock SCALER_PLLIN_CLK>, 546 <&clock VIF_PLLIN_CLK>, 547 <&clock SCALER_CLK>, 548 <&clock VIF0_PRE_CLK>, 549 <&clock CODEC_CLK>, 550 <&clock DITHER_CLK>; 551 assigned-clock-parents = <&cru SCLK_I2S1_OUT>, 552 <&clock LCDC0_CLK>, 553 <&clock SCALER_PLL_CLK>, 554 <&clock VIF_PLL_CLK>, 555 <&cru SCLK_I2S1_OUT>, 556 <&clock VIF0_CLK>; 557 #clock-cells = <1>; 558 status = "okay"; 559 }; 560 561 dsi { 562 compatible = "rockchip,rk618-dsi"; 563 clocks = <&clock MIPI_CLK>; 564 clock-names = "dsi"; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 status = "okay"; 568 569 ports { 570 #address-cells = <1>; 571 #size-cells = <0>; 572 573 port@0 { 574 reg = <0>; 575 576 dsi_in_rgb: endpoint { 577 remote-endpoint = <&rgb_out_dsi>; 578 }; 579 }; 580 }; 581 582 panel@0 { 583 compatible = "simple-panel-dsi"; 584 reg = <0>; 585 power-supply = <&vcc3v3_lcd>; 586 backlight = <&backlight>; 587 reset-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; 588 prepare-delay-ms = <20>; 589 reset-delay-ms = <20>; 590 init-delay-ms = <20>; 591 enable-delay-ms = <120>; 592 disable-delay-ms = <20>; 593 unprepare-delay-ms = <20>; 594 595 width-mm = <95>; 596 height-mm = <151>; 597 598 dsi,flags = <(MIPI_DSI_MODE_VIDEO | 599 MIPI_DSI_MODE_VIDEO_BURST | 600 MIPI_DSI_MODE_LPM | 601 MIPI_DSI_MODE_EOT_PACKET)>; 602 dsi,format = <MIPI_DSI_FMT_RGB888>; 603 dsi,lanes = <4>; 604 605 panel-init-sequence = [ 606 15 00 02 b0 00 607 15 00 02 d6 01 608 39 00 06 b3 14 08 00 22 00 609 15 00 02 b4 0c 610 15 00 02 DE 00 611 39 00 03 b6 3a d3 612 15 00 02 51 E0 613 15 00 02 53 04 614 15 00 02 3a 77 615 15 00 02 35 01 616 39 00 05 2A 00 00 04 AF 617 39 00 05 2B 00 00 07 7F 618 05 96 01 29 619 05 14 01 11 620 ]; 621 622 panel-exit-sequence = [ 623 05 00 01 28 624 05 00 01 10 625 ]; 626 627 display-timings { 628 native-mode = <&timing1>; 629 630 timing1: timing1 { 631 clock-frequency = <156000000>; 632 hactive = <1200>; 633 vactive = <1920>; 634 hback-porch = <60>; 635 hfront-porch = <80>; 636 vback-porch = <4>; 637 vfront-porch = <4>; 638 hsync-len = <10>; 639 vsync-len = <1>; 640 hsync-active = <0>; 641 vsync-active = <0>; 642 de-active = <0>; 643 pixelclk-active = <0>; 644 }; 645 }; 646 }; 647 }; 648 }; 649}; 650 651&io_domains { 652 vccio1-supply = <&vcc1v8_soc>; 653 vccio2-supply = <&vccio_sd>; 654 vccio3-supply = <&vcc_3v0>; 655 vccio4-supply = <&vcc3v0_pmu>; 656 vccio5-supply = <&vcc_3v0>; 657 status = "okay"; 658}; 659 660&nandc0 { 661 status = "okay"; 662}; 663 664&pmu_io_domains { 665 status = "okay"; 666 667 pmuio1-supply = <&vcc3v0_pmu>; 668 pmuio2-supply = <&vcc3v0_pmu>; 669}; 670 671&pwm0 { 672 status = "okay"; 673}; 674 675&rk_rga { 676 status = "okay"; 677}; 678 679&rockchip_suspend { 680 rockchip,sleep-debug-en = <1>; 681 status = "okay"; 682}; 683 684&saradc { 685 vref-supply = <&vcc1v8_soc>; 686 status = "okay"; 687}; 688 689&sdmmc { 690 bus-width = <4>; 691 cap-mmc-highspeed; 692 cap-sd-highspeed; 693 no-sdio; 694 no-mmc; 695 card-detect-delay = <800>; 696 ignore-pm-notify; 697 sd-uhs-sdr12; 698 sd-uhs-sdr25; 699 sd-uhs-sdr50; 700 sd-uhs-sdr104; 701 vqmmc-supply = <&vccio_sd>; 702 vmmc-supply = <&vcc_sd>; 703 status = "okay"; 704}; 705 706&sdio { 707 bus-width = <4>; 708 cap-sd-highspeed; 709 no-sd; 710 no-mmc; 711 ignore-pm-notify; 712 keep-power-in-suspend; 713 non-removable; 714 mmc-pwrseq = <&sdio_pwrseq>; 715 sd-uhs-sdr104; 716 status = "okay"; 717}; 718 719&tsadc { 720 pinctrl-names = "init", "default"; 721 pinctrl-0 = <&tsadc_otp_gpio>; 722 pinctrl-1 = <&tsadc_otp_out>; 723 status = "okay"; 724}; 725 726&uart1 { 727 pinctrl-names = "default"; 728 pinctrl-0 = <&uart1_xfer &uart1_cts>; 729 status = "okay"; 730}; 731 732&u2phy { 733 status = "okay"; 734 735 u2phy_host: host-port { 736 status = "okay"; 737 }; 738 739 u2phy_otg: otg-port { 740 status = "okay"; 741 }; 742}; 743 744&usb20_otg { 745 status = "okay"; 746}; 747 748&usb_host0_ehci { 749 status = "okay"; 750}; 751 752&usb_host0_ohci { 753 status = "okay"; 754}; 755 756&vopb { 757 status = "okay"; 758}; 759 760&vopb_mmu { 761 status = "okay"; 762}; 763 764&vopl { 765 status = "okay"; 766}; 767 768&vopl_mmu { 769 status = "okay"; 770}; 771 772&mpp_srv { 773 status = "okay"; 774}; 775 776&vdpu { 777 status = "okay"; 778}; 779 780&vepu { 781 status = "okay"; 782}; 783 784&vpu_mmu { 785 status = "okay"; 786}; 787 788&hevc { 789 status = "okay"; 790}; 791 792&hevc_mmu { 793 status = "okay"; 794}; 795 796&rgb { 797 status = "okay"; 798 799 ports { 800 port@1 { 801 reg = <1>; 802 803 rgb_out_dsi: endpoint { 804 remote-endpoint = <&dsi_in_rgb>; 805 }; 806 }; 807 }; 808}; 809 810&rgb_in_vopl { 811 status = "okay"; 812}; 813 814&rgb_in_vopb { 815 status = "disabled"; 816}; 817 818&route_rgb { 819 connect = <&vopl_out_rgb>; 820 status = "okay"; 821}; 822 823&pinctrl { 824 pmic { 825 pmic_int: pmic_int { 826 rockchip,pins = 827 <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 828 }; 829 830 soc_slppin_gpio: soc_slppin_gpio { 831 rockchip,pins = 832 <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 833 }; 834 835 soc_slppin_slp: soc_slppin_slp { 836 rockchip,pins = 837 <0 RK_PA4 1 &pcfg_pull_none>; 838 }; 839 840 soc_slppin_rst: soc_slppin_rst { 841 rockchip,pins = 842 <0 RK_PA4 2 &pcfg_pull_none>; 843 }; 844 }; 845 846 sdio-pwrseq { 847 wifi_enable_h: wifi-enable-h { 848 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 849 }; 850 }; 851}; 852 853&firmware_android { 854 compatible = "android,firmware"; 855 856 fstab { 857 compatible = "android,fstab"; 858 859 system { 860 compatible = "android,system"; 861 dev = "/dev/block/by-name/system"; 862 type = "ext4"; 863 mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 864 fsmgr_flags = "wait"; 865 }; 866 867 vendor { 868 compatible = "android,vendor"; 869 dev = "/dev/block/by-name/vendor"; 870 type = "ext4"; 871 mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 872 fsmgr_flags = "wait"; 873 }; 874 }; 875}; 876