1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 11*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 12*4882a593Smuzhiyun#include <dt-bindings/clock/rk618-cru.h> 13*4882a593Smuzhiyun#include "px30.dtsi" 14*4882a593Smuzhiyun#include "px30-android.dtsi" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun model = "Rockchip PX30 Z7 A0 board"; 18*4882a593Smuzhiyun compatible = "rockchip,px30-z7-a0", "rockchip,px30"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun adc-keys { 21*4882a593Smuzhiyun compatible = "adc-keys"; 22*4882a593Smuzhiyun io-channels = <&saradc 2>; 23*4882a593Smuzhiyun io-channel-names = "buttons"; 24*4882a593Smuzhiyun poll-interval = <100>; 25*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun esc-key { 28*4882a593Smuzhiyun linux,code = <KEY_ESC>; 29*4882a593Smuzhiyun label = "esc"; 30*4882a593Smuzhiyun press-threshold-microvolt = <1310000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun home-key { 34*4882a593Smuzhiyun linux,code = <KEY_HOME>; 35*4882a593Smuzhiyun label = "home"; 36*4882a593Smuzhiyun press-threshold-microvolt = <624000>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun menu-key { 40*4882a593Smuzhiyun linux,code = <KEY_MENU>; 41*4882a593Smuzhiyun label = "menu"; 42*4882a593Smuzhiyun press-threshold-microvolt = <987000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun vol-down-key { 46*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 47*4882a593Smuzhiyun label = "volume down"; 48*4882a593Smuzhiyun press-threshold-microvolt = <300000>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun vol-up-key { 52*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 53*4882a593Smuzhiyun label = "volume up"; 54*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun backlight: backlight { 59*4882a593Smuzhiyun compatible = "pwm-backlight"; 60*4882a593Smuzhiyun pwms = <&pwm0 0 25000 0>; 61*4882a593Smuzhiyun brightness-levels = < 62*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 63*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 64*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 65*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 66*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 67*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 68*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 69*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 70*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 71*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 72*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 73*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 74*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 75*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 76*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 77*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 78*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 79*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 80*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 81*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 82*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 83*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 84*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 85*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 86*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 87*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 88*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 89*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 90*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 91*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 92*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 93*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 94*4882a593Smuzhiyun default-brightness-level = <200>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 98*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 99*4882a593Smuzhiyun pinctrl-names = "default"; 100*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * On the module itself this is one of these (depending 104*4882a593Smuzhiyun * on the actual card populated): 105*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 106*4882a593Smuzhiyun * - PDN (power down when low) 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 112*4882a593Smuzhiyun compatible = "regulator-fixed"; 113*4882a593Smuzhiyun regulator-name = "vcc_phy"; 114*4882a593Smuzhiyun regulator-always-on; 115*4882a593Smuzhiyun regulator-boot-on; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun vcc5v0_sys: vccsys { 119*4882a593Smuzhiyun compatible = "regulator-fixed"; 120*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 121*4882a593Smuzhiyun regulator-always-on; 122*4882a593Smuzhiyun regulator-boot-on; 123*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 124*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&display_subsystem { 129*4882a593Smuzhiyun status = "okay"; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&dsi { 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun panel@0 { 136*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 137*4882a593Smuzhiyun reg = <0>; 138*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd>; 139*4882a593Smuzhiyun backlight = <&backlight>; 140*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; 141*4882a593Smuzhiyun prepare-delay-ms = <20>; 142*4882a593Smuzhiyun reset-delay-ms = <20>; 143*4882a593Smuzhiyun init-delay-ms = <20>; 144*4882a593Smuzhiyun enable-delay-ms = <120>; 145*4882a593Smuzhiyun disable-delay-ms = <20>; 146*4882a593Smuzhiyun unprepare-delay-ms = <20>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun width-mm = <95>; 149*4882a593Smuzhiyun height-mm = <151>; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 152*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 153*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 154*4882a593Smuzhiyun dsi,lanes = <4>; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun panel-init-sequence = [ 157*4882a593Smuzhiyun 15 00 02 b0 00 158*4882a593Smuzhiyun 15 00 02 d6 01 159*4882a593Smuzhiyun 39 00 06 b3 14 08 00 22 00 160*4882a593Smuzhiyun 15 00 02 b4 0c 161*4882a593Smuzhiyun 15 00 02 de 00 162*4882a593Smuzhiyun 39 00 03 b6 3a d3 163*4882a593Smuzhiyun 15 00 02 51 e0 164*4882a593Smuzhiyun 15 00 02 53 04 165*4882a593Smuzhiyun 15 00 02 3a 77 166*4882a593Smuzhiyun 15 00 02 35 01 167*4882a593Smuzhiyun 39 00 05 2a 00 00 04 af 168*4882a593Smuzhiyun 39 00 05 2b 00 00 07 7f 169*4882a593Smuzhiyun 05 96 01 29 170*4882a593Smuzhiyun 05 14 01 11 171*4882a593Smuzhiyun ]; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun panel-exit-sequence = [ 174*4882a593Smuzhiyun 05 00 01 28 175*4882a593Smuzhiyun 05 00 01 10 176*4882a593Smuzhiyun ]; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun display-timings { 179*4882a593Smuzhiyun native-mode = <&timing0>; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun timing0: timing0 { 182*4882a593Smuzhiyun clock-frequency = <156000000>; 183*4882a593Smuzhiyun hactive = <1200>; 184*4882a593Smuzhiyun vactive = <1920>; 185*4882a593Smuzhiyun hback-porch = <60>; 186*4882a593Smuzhiyun hfront-porch = <80>; 187*4882a593Smuzhiyun vback-porch = <4>; 188*4882a593Smuzhiyun vfront-porch = <4>; 189*4882a593Smuzhiyun hsync-len = <10>; 190*4882a593Smuzhiyun vsync-len = <1>; 191*4882a593Smuzhiyun hsync-active = <0>; 192*4882a593Smuzhiyun vsync-active = <0>; 193*4882a593Smuzhiyun de-active = <0>; 194*4882a593Smuzhiyun pixelclk-active = <0>; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun ports { 199*4882a593Smuzhiyun #address-cells = <1>; 200*4882a593Smuzhiyun #size-cells = <0>; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun port@0 { 203*4882a593Smuzhiyun reg = <0>; 204*4882a593Smuzhiyun panel_in_dsi: endpoint { 205*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun ports { 212*4882a593Smuzhiyun #address-cells = <1>; 213*4882a593Smuzhiyun #size-cells = <0>; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun port@1 { 216*4882a593Smuzhiyun reg = <1>; 217*4882a593Smuzhiyun dsi_out_panel: endpoint { 218*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun}; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun&dsi_in_vopb { 225*4882a593Smuzhiyun status = "okay"; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&dsi_in_vopl { 229*4882a593Smuzhiyun status = "disabled"; 230*4882a593Smuzhiyun}; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun&route_dsi { 233*4882a593Smuzhiyun connect = <&vopb_out_dsi>; 234*4882a593Smuzhiyun status = "okay"; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&bus_apll { 238*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&cpu0 { 243*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 244*4882a593Smuzhiyun}; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun&dfi { 247*4882a593Smuzhiyun status = "okay"; 248*4882a593Smuzhiyun}; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun&dmc { 251*4882a593Smuzhiyun center-supply = <&vdd_logic>; 252*4882a593Smuzhiyun auto-freq-en = <0>; 253*4882a593Smuzhiyun status = "okay"; 254*4882a593Smuzhiyun}; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun&emmc { 257*4882a593Smuzhiyun bus-width = <8>; 258*4882a593Smuzhiyun cap-mmc-highspeed; 259*4882a593Smuzhiyun mmc-hs200-1_8v; 260*4882a593Smuzhiyun no-sdio; 261*4882a593Smuzhiyun no-sd; 262*4882a593Smuzhiyun disable-wp; 263*4882a593Smuzhiyun non-removable; 264*4882a593Smuzhiyun num-slots = <1>; 265*4882a593Smuzhiyun status = "okay"; 266*4882a593Smuzhiyun}; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun&gpu { 269*4882a593Smuzhiyun mali-supply = <&vdd_logic>; 270*4882a593Smuzhiyun status = "okay"; 271*4882a593Smuzhiyun}; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun&i2c0 { 274*4882a593Smuzhiyun status = "okay"; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun rk809: pmic@20 { 277*4882a593Smuzhiyun compatible = "rockchip,rk809"; 278*4882a593Smuzhiyun reg = <0x20>; 279*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 280*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 281*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 282*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 283*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 284*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 285*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 286*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 287*4882a593Smuzhiyun rockchip,system-power-controller; 288*4882a593Smuzhiyun wakeup-source; 289*4882a593Smuzhiyun #clock-cells = <1>; 290*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 291*4882a593Smuzhiyun pmic-reset-func = <1>; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun vcc1-supply = <&vcc5v0_sys>; 294*4882a593Smuzhiyun vcc2-supply = <&vcc5v0_sys>; 295*4882a593Smuzhiyun vcc3-supply = <&vcc5v0_sys>; 296*4882a593Smuzhiyun vcc4-supply = <&vcc5v0_sys>; 297*4882a593Smuzhiyun vcc5-supply = <&vcc3v3_sys>; 298*4882a593Smuzhiyun vcc6-supply = <&vcc3v3_sys>; 299*4882a593Smuzhiyun vcc7-supply = <&vcc3v3_sys>; 300*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 301*4882a593Smuzhiyun vcc9-supply = <&vcc5v0_sys>; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun pwrkey { 304*4882a593Smuzhiyun status = "okay"; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 308*4882a593Smuzhiyun gpio-controller; 309*4882a593Smuzhiyun #gpio-cells = <2>; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 312*4882a593Smuzhiyun pins = "gpio_slp"; 313*4882a593Smuzhiyun function = "pin_fun0"; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 317*4882a593Smuzhiyun pins = "gpio_slp"; 318*4882a593Smuzhiyun function = "pin_fun1"; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 322*4882a593Smuzhiyun pins = "gpio_slp"; 323*4882a593Smuzhiyun function = "pin_fun2"; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 327*4882a593Smuzhiyun pins = "gpio_slp"; 328*4882a593Smuzhiyun function = "pin_fun3"; 329*4882a593Smuzhiyun }; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun regulators { 333*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 334*4882a593Smuzhiyun regulator-always-on; 335*4882a593Smuzhiyun regulator-boot-on; 336*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 337*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 338*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 339*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 340*4882a593Smuzhiyun regulator-name = "vdd_logic"; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun regulator-state-mem { 343*4882a593Smuzhiyun regulator-on-in-suspend; 344*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun }; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 349*4882a593Smuzhiyun regulator-always-on; 350*4882a593Smuzhiyun regulator-boot-on; 351*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 352*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 353*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 354*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 355*4882a593Smuzhiyun regulator-name = "vdd_arm"; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun regulator-state-mem { 358*4882a593Smuzhiyun regulator-off-in-suspend; 359*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 360*4882a593Smuzhiyun }; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 364*4882a593Smuzhiyun regulator-always-on; 365*4882a593Smuzhiyun regulator-boot-on; 366*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 367*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun regulator-state-mem { 370*4882a593Smuzhiyun regulator-on-in-suspend; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun vcc_3v0: DCDC_REG4 { 375*4882a593Smuzhiyun regulator-always-on; 376*4882a593Smuzhiyun regulator-boot-on; 377*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 378*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 379*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 380*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun regulator-state-mem { 383*4882a593Smuzhiyun regulator-on-in-suspend; 384*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 385*4882a593Smuzhiyun }; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun vcc_1v0: LDO_REG1 { 389*4882a593Smuzhiyun regulator-always-on; 390*4882a593Smuzhiyun regulator-boot-on; 391*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 392*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 393*4882a593Smuzhiyun regulator-name = "vcc_1v0"; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun regulator-state-mem { 396*4882a593Smuzhiyun regulator-on-in-suspend; 397*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun vcc1v8_soc: LDO_REG2 { 402*4882a593Smuzhiyun regulator-always-on; 403*4882a593Smuzhiyun regulator-boot-on; 404*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 405*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 406*4882a593Smuzhiyun regulator-name = "vcc1v8_soc"; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun regulator-state-mem { 409*4882a593Smuzhiyun regulator-on-in-suspend; 410*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun vdd1v0_soc: LDO_REG3 { 415*4882a593Smuzhiyun regulator-always-on; 416*4882a593Smuzhiyun regulator-boot-on; 417*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 418*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 419*4882a593Smuzhiyun regulator-name = "vcc1v0_soc"; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun regulator-state-mem { 422*4882a593Smuzhiyun regulator-on-in-suspend; 423*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun vcc3v0_pmu: LDO_REG4 { 428*4882a593Smuzhiyun regulator-always-on; 429*4882a593Smuzhiyun regulator-boot-on; 430*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 431*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 432*4882a593Smuzhiyun regulator-name = "vcc3v0_pmu"; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun regulator-state-mem { 435*4882a593Smuzhiyun regulator-on-in-suspend; 436*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 441*4882a593Smuzhiyun regulator-always-on; 442*4882a593Smuzhiyun regulator-boot-on; 443*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 444*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 445*4882a593Smuzhiyun regulator-name = "vccio_sd"; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun regulator-state-mem { 448*4882a593Smuzhiyun regulator-on-in-suspend; 449*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun vcc_sd: LDO_REG6 { 454*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 455*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 456*4882a593Smuzhiyun regulator-name = "vcc_sd"; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun regulator-state-mem { 459*4882a593Smuzhiyun regulator-on-in-suspend; 460*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 461*4882a593Smuzhiyun }; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG7 { 465*4882a593Smuzhiyun regulator-always-on; 466*4882a593Smuzhiyun regulator-boot-on; 467*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 468*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 469*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun regulator-state-mem { 472*4882a593Smuzhiyun regulator-off-in-suspend; 473*4882a593Smuzhiyun regulator-suspend-microvolt = <2800000>; 474*4882a593Smuzhiyun }; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 478*4882a593Smuzhiyun regulator-always-on; 479*4882a593Smuzhiyun regulator-boot-on; 480*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 481*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 482*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun regulator-state-mem { 485*4882a593Smuzhiyun regulator-on-in-suspend; 486*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun }; 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun vdd1v5_dvp: LDO_REG9 { 491*4882a593Smuzhiyun regulator-always-on; 492*4882a593Smuzhiyun regulator-boot-on; 493*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 494*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 495*4882a593Smuzhiyun regulator-name = "vdd1v5_dvp"; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun regulator-state-mem { 498*4882a593Smuzhiyun regulator-off-in-suspend; 499*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 500*4882a593Smuzhiyun }; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun vcc3v3_sys: DCDC_REG5 { 504*4882a593Smuzhiyun regulator-always-on; 505*4882a593Smuzhiyun regulator-boot-on; 506*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 507*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 508*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun regulator-state-mem { 511*4882a593Smuzhiyun regulator-on-in-suspend; 512*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun vcc5v0_host: SWITCH_REG1 { 517*4882a593Smuzhiyun regulator-always-on; 518*4882a593Smuzhiyun regulator-boot-on; 519*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun vcc3v3_lcd: SWITCH_REG2 { 523*4882a593Smuzhiyun regulator-boot-on; 524*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd"; 525*4882a593Smuzhiyun }; 526*4882a593Smuzhiyun }; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun rk618@50 { 530*4882a593Smuzhiyun compatible = "rockchip,rk618"; 531*4882a593Smuzhiyun reg = <0x50>; 532*4882a593Smuzhiyun pinctrl-names = "default"; 533*4882a593Smuzhiyun pinctrl-0 = <&i2s1_2ch_mclk>; 534*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>; 535*4882a593Smuzhiyun clock-names = "clkin"; 536*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_I2S1_OUT>; 537*4882a593Smuzhiyun assigned-clock-rates = <12000000>; 538*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; 539*4882a593Smuzhiyun status = "okay"; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun clock: cru { 542*4882a593Smuzhiyun compatible = "rockchip,rk618-cru"; 543*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; 544*4882a593Smuzhiyun clock-names = "clkin", "lcdc0_dclkp"; 545*4882a593Smuzhiyun assigned-clocks = <&clock SCALER_PLLIN_CLK>, 546*4882a593Smuzhiyun <&clock VIF_PLLIN_CLK>, 547*4882a593Smuzhiyun <&clock SCALER_CLK>, 548*4882a593Smuzhiyun <&clock VIF0_PRE_CLK>, 549*4882a593Smuzhiyun <&clock CODEC_CLK>, 550*4882a593Smuzhiyun <&clock DITHER_CLK>; 551*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_I2S1_OUT>, 552*4882a593Smuzhiyun <&clock LCDC0_CLK>, 553*4882a593Smuzhiyun <&clock SCALER_PLL_CLK>, 554*4882a593Smuzhiyun <&clock VIF_PLL_CLK>, 555*4882a593Smuzhiyun <&cru SCLK_I2S1_OUT>, 556*4882a593Smuzhiyun <&clock VIF0_CLK>; 557*4882a593Smuzhiyun #clock-cells = <1>; 558*4882a593Smuzhiyun status = "okay"; 559*4882a593Smuzhiyun }; 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun dsi { 562*4882a593Smuzhiyun compatible = "rockchip,rk618-dsi"; 563*4882a593Smuzhiyun clocks = <&clock MIPI_CLK>; 564*4882a593Smuzhiyun clock-names = "dsi"; 565*4882a593Smuzhiyun #address-cells = <1>; 566*4882a593Smuzhiyun #size-cells = <0>; 567*4882a593Smuzhiyun status = "okay"; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun ports { 570*4882a593Smuzhiyun #address-cells = <1>; 571*4882a593Smuzhiyun #size-cells = <0>; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun port@0 { 574*4882a593Smuzhiyun reg = <0>; 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun dsi_in_rgb: endpoint { 577*4882a593Smuzhiyun remote-endpoint = <&rgb_out_dsi>; 578*4882a593Smuzhiyun }; 579*4882a593Smuzhiyun }; 580*4882a593Smuzhiyun }; 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun panel@0 { 583*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 584*4882a593Smuzhiyun reg = <0>; 585*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd>; 586*4882a593Smuzhiyun backlight = <&backlight>; 587*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; 588*4882a593Smuzhiyun prepare-delay-ms = <20>; 589*4882a593Smuzhiyun reset-delay-ms = <20>; 590*4882a593Smuzhiyun init-delay-ms = <20>; 591*4882a593Smuzhiyun enable-delay-ms = <120>; 592*4882a593Smuzhiyun disable-delay-ms = <20>; 593*4882a593Smuzhiyun unprepare-delay-ms = <20>; 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun width-mm = <95>; 596*4882a593Smuzhiyun height-mm = <151>; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | 599*4882a593Smuzhiyun MIPI_DSI_MODE_VIDEO_BURST | 600*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | 601*4882a593Smuzhiyun MIPI_DSI_MODE_EOT_PACKET)>; 602*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 603*4882a593Smuzhiyun dsi,lanes = <4>; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun panel-init-sequence = [ 606*4882a593Smuzhiyun 15 00 02 b0 00 607*4882a593Smuzhiyun 15 00 02 d6 01 608*4882a593Smuzhiyun 39 00 06 b3 14 08 00 22 00 609*4882a593Smuzhiyun 15 00 02 b4 0c 610*4882a593Smuzhiyun 15 00 02 DE 00 611*4882a593Smuzhiyun 39 00 03 b6 3a d3 612*4882a593Smuzhiyun 15 00 02 51 E0 613*4882a593Smuzhiyun 15 00 02 53 04 614*4882a593Smuzhiyun 15 00 02 3a 77 615*4882a593Smuzhiyun 15 00 02 35 01 616*4882a593Smuzhiyun 39 00 05 2A 00 00 04 AF 617*4882a593Smuzhiyun 39 00 05 2B 00 00 07 7F 618*4882a593Smuzhiyun 05 96 01 29 619*4882a593Smuzhiyun 05 14 01 11 620*4882a593Smuzhiyun ]; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun panel-exit-sequence = [ 623*4882a593Smuzhiyun 05 00 01 28 624*4882a593Smuzhiyun 05 00 01 10 625*4882a593Smuzhiyun ]; 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun display-timings { 628*4882a593Smuzhiyun native-mode = <&timing1>; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun timing1: timing1 { 631*4882a593Smuzhiyun clock-frequency = <156000000>; 632*4882a593Smuzhiyun hactive = <1200>; 633*4882a593Smuzhiyun vactive = <1920>; 634*4882a593Smuzhiyun hback-porch = <60>; 635*4882a593Smuzhiyun hfront-porch = <80>; 636*4882a593Smuzhiyun vback-porch = <4>; 637*4882a593Smuzhiyun vfront-porch = <4>; 638*4882a593Smuzhiyun hsync-len = <10>; 639*4882a593Smuzhiyun vsync-len = <1>; 640*4882a593Smuzhiyun hsync-active = <0>; 641*4882a593Smuzhiyun vsync-active = <0>; 642*4882a593Smuzhiyun de-active = <0>; 643*4882a593Smuzhiyun pixelclk-active = <0>; 644*4882a593Smuzhiyun }; 645*4882a593Smuzhiyun }; 646*4882a593Smuzhiyun }; 647*4882a593Smuzhiyun }; 648*4882a593Smuzhiyun }; 649*4882a593Smuzhiyun}; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun&io_domains { 652*4882a593Smuzhiyun vccio1-supply = <&vcc1v8_soc>; 653*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 654*4882a593Smuzhiyun vccio3-supply = <&vcc_3v0>; 655*4882a593Smuzhiyun vccio4-supply = <&vcc3v0_pmu>; 656*4882a593Smuzhiyun vccio5-supply = <&vcc_3v0>; 657*4882a593Smuzhiyun status = "okay"; 658*4882a593Smuzhiyun}; 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun&nandc0 { 661*4882a593Smuzhiyun status = "okay"; 662*4882a593Smuzhiyun}; 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun&pmu_io_domains { 665*4882a593Smuzhiyun status = "okay"; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun pmuio1-supply = <&vcc3v0_pmu>; 668*4882a593Smuzhiyun pmuio2-supply = <&vcc3v0_pmu>; 669*4882a593Smuzhiyun}; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun&pwm0 { 672*4882a593Smuzhiyun status = "okay"; 673*4882a593Smuzhiyun}; 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun&rk_rga { 676*4882a593Smuzhiyun status = "okay"; 677*4882a593Smuzhiyun}; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun&rockchip_suspend { 680*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 681*4882a593Smuzhiyun status = "okay"; 682*4882a593Smuzhiyun}; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun&saradc { 685*4882a593Smuzhiyun vref-supply = <&vcc1v8_soc>; 686*4882a593Smuzhiyun status = "okay"; 687*4882a593Smuzhiyun}; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun&sdmmc { 690*4882a593Smuzhiyun bus-width = <4>; 691*4882a593Smuzhiyun cap-mmc-highspeed; 692*4882a593Smuzhiyun cap-sd-highspeed; 693*4882a593Smuzhiyun no-sdio; 694*4882a593Smuzhiyun no-mmc; 695*4882a593Smuzhiyun card-detect-delay = <800>; 696*4882a593Smuzhiyun ignore-pm-notify; 697*4882a593Smuzhiyun sd-uhs-sdr12; 698*4882a593Smuzhiyun sd-uhs-sdr25; 699*4882a593Smuzhiyun sd-uhs-sdr50; 700*4882a593Smuzhiyun sd-uhs-sdr104; 701*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 702*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 703*4882a593Smuzhiyun status = "okay"; 704*4882a593Smuzhiyun}; 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun&sdio { 707*4882a593Smuzhiyun bus-width = <4>; 708*4882a593Smuzhiyun cap-sd-highspeed; 709*4882a593Smuzhiyun no-sd; 710*4882a593Smuzhiyun no-mmc; 711*4882a593Smuzhiyun ignore-pm-notify; 712*4882a593Smuzhiyun keep-power-in-suspend; 713*4882a593Smuzhiyun non-removable; 714*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 715*4882a593Smuzhiyun sd-uhs-sdr104; 716*4882a593Smuzhiyun status = "okay"; 717*4882a593Smuzhiyun}; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun&tsadc { 720*4882a593Smuzhiyun pinctrl-names = "init", "default"; 721*4882a593Smuzhiyun pinctrl-0 = <&tsadc_otp_gpio>; 722*4882a593Smuzhiyun pinctrl-1 = <&tsadc_otp_out>; 723*4882a593Smuzhiyun status = "okay"; 724*4882a593Smuzhiyun}; 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun&uart1 { 727*4882a593Smuzhiyun pinctrl-names = "default"; 728*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer &uart1_cts>; 729*4882a593Smuzhiyun status = "okay"; 730*4882a593Smuzhiyun}; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun&u2phy { 733*4882a593Smuzhiyun status = "okay"; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun u2phy_host: host-port { 736*4882a593Smuzhiyun status = "okay"; 737*4882a593Smuzhiyun }; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun u2phy_otg: otg-port { 740*4882a593Smuzhiyun status = "okay"; 741*4882a593Smuzhiyun }; 742*4882a593Smuzhiyun}; 743*4882a593Smuzhiyun 744*4882a593Smuzhiyun&usb20_otg { 745*4882a593Smuzhiyun status = "okay"; 746*4882a593Smuzhiyun}; 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun&usb_host0_ehci { 749*4882a593Smuzhiyun status = "okay"; 750*4882a593Smuzhiyun}; 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun&usb_host0_ohci { 753*4882a593Smuzhiyun status = "okay"; 754*4882a593Smuzhiyun}; 755*4882a593Smuzhiyun 756*4882a593Smuzhiyun&vopb { 757*4882a593Smuzhiyun status = "okay"; 758*4882a593Smuzhiyun}; 759*4882a593Smuzhiyun 760*4882a593Smuzhiyun&vopb_mmu { 761*4882a593Smuzhiyun status = "okay"; 762*4882a593Smuzhiyun}; 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun&vopl { 765*4882a593Smuzhiyun status = "okay"; 766*4882a593Smuzhiyun}; 767*4882a593Smuzhiyun 768*4882a593Smuzhiyun&vopl_mmu { 769*4882a593Smuzhiyun status = "okay"; 770*4882a593Smuzhiyun}; 771*4882a593Smuzhiyun 772*4882a593Smuzhiyun&mpp_srv { 773*4882a593Smuzhiyun status = "okay"; 774*4882a593Smuzhiyun}; 775*4882a593Smuzhiyun 776*4882a593Smuzhiyun&vdpu { 777*4882a593Smuzhiyun status = "okay"; 778*4882a593Smuzhiyun}; 779*4882a593Smuzhiyun 780*4882a593Smuzhiyun&vepu { 781*4882a593Smuzhiyun status = "okay"; 782*4882a593Smuzhiyun}; 783*4882a593Smuzhiyun 784*4882a593Smuzhiyun&vpu_mmu { 785*4882a593Smuzhiyun status = "okay"; 786*4882a593Smuzhiyun}; 787*4882a593Smuzhiyun 788*4882a593Smuzhiyun&hevc { 789*4882a593Smuzhiyun status = "okay"; 790*4882a593Smuzhiyun}; 791*4882a593Smuzhiyun 792*4882a593Smuzhiyun&hevc_mmu { 793*4882a593Smuzhiyun status = "okay"; 794*4882a593Smuzhiyun}; 795*4882a593Smuzhiyun 796*4882a593Smuzhiyun&rgb { 797*4882a593Smuzhiyun status = "okay"; 798*4882a593Smuzhiyun 799*4882a593Smuzhiyun ports { 800*4882a593Smuzhiyun port@1 { 801*4882a593Smuzhiyun reg = <1>; 802*4882a593Smuzhiyun 803*4882a593Smuzhiyun rgb_out_dsi: endpoint { 804*4882a593Smuzhiyun remote-endpoint = <&dsi_in_rgb>; 805*4882a593Smuzhiyun }; 806*4882a593Smuzhiyun }; 807*4882a593Smuzhiyun }; 808*4882a593Smuzhiyun}; 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun&rgb_in_vopl { 811*4882a593Smuzhiyun status = "okay"; 812*4882a593Smuzhiyun}; 813*4882a593Smuzhiyun 814*4882a593Smuzhiyun&rgb_in_vopb { 815*4882a593Smuzhiyun status = "disabled"; 816*4882a593Smuzhiyun}; 817*4882a593Smuzhiyun 818*4882a593Smuzhiyun&route_rgb { 819*4882a593Smuzhiyun connect = <&vopl_out_rgb>; 820*4882a593Smuzhiyun status = "okay"; 821*4882a593Smuzhiyun}; 822*4882a593Smuzhiyun 823*4882a593Smuzhiyun&pinctrl { 824*4882a593Smuzhiyun pmic { 825*4882a593Smuzhiyun pmic_int: pmic_int { 826*4882a593Smuzhiyun rockchip,pins = 827*4882a593Smuzhiyun <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 828*4882a593Smuzhiyun }; 829*4882a593Smuzhiyun 830*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 831*4882a593Smuzhiyun rockchip,pins = 832*4882a593Smuzhiyun <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 833*4882a593Smuzhiyun }; 834*4882a593Smuzhiyun 835*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 836*4882a593Smuzhiyun rockchip,pins = 837*4882a593Smuzhiyun <0 RK_PA4 1 &pcfg_pull_none>; 838*4882a593Smuzhiyun }; 839*4882a593Smuzhiyun 840*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 841*4882a593Smuzhiyun rockchip,pins = 842*4882a593Smuzhiyun <0 RK_PA4 2 &pcfg_pull_none>; 843*4882a593Smuzhiyun }; 844*4882a593Smuzhiyun }; 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun sdio-pwrseq { 847*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 848*4882a593Smuzhiyun rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 849*4882a593Smuzhiyun }; 850*4882a593Smuzhiyun }; 851*4882a593Smuzhiyun}; 852*4882a593Smuzhiyun 853*4882a593Smuzhiyun&firmware_android { 854*4882a593Smuzhiyun compatible = "android,firmware"; 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun fstab { 857*4882a593Smuzhiyun compatible = "android,fstab"; 858*4882a593Smuzhiyun 859*4882a593Smuzhiyun system { 860*4882a593Smuzhiyun compatible = "android,system"; 861*4882a593Smuzhiyun dev = "/dev/block/by-name/system"; 862*4882a593Smuzhiyun type = "ext4"; 863*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 864*4882a593Smuzhiyun fsmgr_flags = "wait"; 865*4882a593Smuzhiyun }; 866*4882a593Smuzhiyun 867*4882a593Smuzhiyun vendor { 868*4882a593Smuzhiyun compatible = "android,vendor"; 869*4882a593Smuzhiyun dev = "/dev/block/by-name/vendor"; 870*4882a593Smuzhiyun type = "ext4"; 871*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 872*4882a593Smuzhiyun fsmgr_flags = "wait"; 873*4882a593Smuzhiyun }; 874*4882a593Smuzhiyun }; 875*4882a593Smuzhiyun}; 876