1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "px30.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun compatible = "rockchip,linux", "rockchip,px30-robot"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun chosen { 12*4882a593Smuzhiyun bootargs = "console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootwait"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun fiq-debugger { 16*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 17*4882a593Smuzhiyun rockchip,serial-id = <2>; 18*4882a593Smuzhiyun rockchip,wake-irq = <0>; 19*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 20*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 21*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 22*4882a593Smuzhiyun interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 23*4882a593Smuzhiyun pinctrl-names = "default"; 24*4882a593Smuzhiyun pinctrl-0 = <&uart2m0_xfer>; 25*4882a593Smuzhiyun status = "okay"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun reserved-memory { 29*4882a593Smuzhiyun #address-cells = <2>; 30*4882a593Smuzhiyun #size-cells = <2>; 31*4882a593Smuzhiyun ranges; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun ramoops: ramoops@8000000 { 34*4882a593Smuzhiyun compatible = "ramoops"; 35*4882a593Smuzhiyun reg = <0x0 0x8000000 0x0 0xa0000>; 36*4882a593Smuzhiyun record-size = <0x20000>; 37*4882a593Smuzhiyun console-size = <0x80000>; 38*4882a593Smuzhiyun ftrace-size = <0x00000>; 39*4882a593Smuzhiyun pmsg-size = <0x00000>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&cpu0_opp_table { 45*4882a593Smuzhiyun /delete-node/ opp-1248000000; 46*4882a593Smuzhiyun /delete-node/ opp-1296000000; 47*4882a593Smuzhiyun /delete-node/ opp-1416000000; 48*4882a593Smuzhiyun /delete-node/ opp-1512000000; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&dmc_opp_table { 52*4882a593Smuzhiyun /delete-node/ opp-666000000; 53*4882a593Smuzhiyun /delete-node/ opp-768000000; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&i2s1_2ch { 57*4882a593Smuzhiyun rockchip,playback-only; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&rng { 61*4882a593Smuzhiyun status = "okay"; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun&soc_thermal { 65*4882a593Smuzhiyun trips { 66*4882a593Smuzhiyun threshold: trip-point-0 { 67*4882a593Smuzhiyun temperature = <75000>; 68*4882a593Smuzhiyun hysteresis = <2000>; 69*4882a593Smuzhiyun type = "passive"; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun target: trip-point-1 { 72*4882a593Smuzhiyun temperature = <90000>; 73*4882a593Smuzhiyun hysteresis = <2000>; 74*4882a593Smuzhiyun type = "passive"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun soc_crit: soc-crit { 77*4882a593Smuzhiyun temperature = <115000>; 78*4882a593Smuzhiyun hysteresis = <2000>; 79*4882a593Smuzhiyun type = "critical"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&tsadc { 85*4882a593Smuzhiyun pinctrl-names = "gpio", "otpout"; 86*4882a593Smuzhiyun pinctrl-0 = <&tsadc_otp_gpio>; 87*4882a593Smuzhiyun pinctrl-1 = <&tsadc_otp_out>; 88*4882a593Smuzhiyun status = "okay"; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&uart2 { 92*4882a593Smuzhiyun status = "disabled"; 93*4882a593Smuzhiyun}; 94