1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6/dts-v1/; 7#include <dt-bindings/clock/rk618-cru.h> 8#include <dt-bindings/display/media-bus-format.h> 9#include "px30-evb-ddr3-v10.dtsi" 10#include "px30-android.dtsi" 11 12&dsi { 13 status = "okay"; 14 15 panel@0 { 16 compatible = "sitronix,st7703", "simple-panel-dsi"; 17 reg = <0>; 18 power-supply = <&vcc3v3_lcd>; 19 backlight = <&backlight>; 20 prepare-delay-ms = <2>; 21 reset-delay-ms = <1>; 22 init-delay-ms = <20>; 23 enable-delay-ms = <120>; 24 disable-delay-ms = <50>; 25 unprepare-delay-ms = <20>; 26 27 width-mm = <68>; 28 height-mm = <121>; 29 30 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 31 MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 32 dsi,format = <MIPI_DSI_FMT_RGB888>; 33 dsi,lanes = <4>; 34 35 panel-init-sequence = [ 36 05 fa 01 11 37 39 00 04 b9 f1 12 83 38 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 39 00 00 00 00 00 44 25 00 91 0a 40 00 00 02 4f 01 00 00 37 41 15 00 02 b8 25 42 39 00 04 bf 02 11 00 43 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 44 00 45 39 00 0a c0 73 73 50 50 00 00 08 70 00 46 15 00 02 bc 46 47 15 00 02 cc 0b 48 15 00 02 b4 80 49 39 00 04 b2 c8 12 30 50 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 51 00 ff 00 c0 10 52 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 53 77 33 33 54 39 00 07 c6 00 00 ff ff 01 ff 55 39 00 03 b5 09 09 56 39 00 03 b6 87 95 57 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 58 23 3f 81 0a a0 37 18 00 80 01 59 00 00 00 00 80 01 00 00 00 48 60 f8 86 42 08 88 88 80 88 88 88 61 58 f8 87 53 18 88 88 81 88 88 62 88 00 00 00 01 00 00 00 00 00 63 00 00 00 00 64 39 00 3e ea 00 1a 00 00 00 00 02 00 00 65 00 00 00 1f 88 81 35 78 88 88 66 85 88 88 88 0f 88 80 24 68 88 67 88 84 88 88 88 23 10 00 00 1c 68 00 00 00 00 00 00 00 00 00 00 69 00 00 00 00 00 30 05 a0 00 00 70 00 00 71 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 72 0c 0d 11 13 12 13 11 18 00 06 73 08 2a 31 3f 38 36 07 0c 0d 11 74 13 12 13 11 18 75 05 32 01 29 76 ]; 77 78 panel-exit-sequence = [ 79 05 00 01 28 80 05 00 01 10 81 ]; 82 83 display-timings { 84 native-mode = <&timing0>; 85 86 timing0: timing0 { 87 clock-frequency = <64000000>; 88 hactive = <720>; 89 vactive = <1280>; 90 hfront-porch = <40>; 91 hsync-len = <10>; 92 hback-porch = <40>; 93 vfront-porch = <22>; 94 vsync-len = <4>; 95 vback-porch = <11>; 96 hsync-active = <0>; 97 vsync-active = <0>; 98 de-active = <0>; 99 pixelclk-active = <0>; 100 }; 101 }; 102 }; 103}; 104 105&dmc { 106 auto-freq-en = <0>; 107}; 108 109&vcc3v0_pmu { 110 regulator-min-microvolt = <3300000>; 111 regulator-max-microvolt = <3300000>; 112 113 regulator-state-mem { 114 regulator-suspend-microvolt = <3300000>; 115 }; 116}; 117 118&i2c1 { 119 120 rk618@50 { 121 compatible = "rockchip,rk618"; 122 reg = <0x50>; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&i2s1_2ch_mclk>; 125 clocks = <&cru SCLK_I2S1_OUT>; 126 clock-names = "clkin"; 127 assigned-clocks = <&cru SCLK_I2S1_OUT>; 128 assigned-clock-rates = <11289600>; 129 reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; 130 status = "okay"; 131 132 clock: cru { 133 compatible = "rockchip,rk618-cru"; 134 clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; 135 clock-names = "clkin", "lcdc0_dclkp"; 136 assigned-clocks = <&clock SCALER_PLLIN_CLK>, 137 <&clock VIF_PLLIN_CLK>, 138 <&clock SCALER_CLK>, 139 <&clock VIF0_PRE_CLK>, 140 <&clock CODEC_CLK>, 141 <&clock DITHER_CLK>; 142 assigned-clock-parents = <&cru SCLK_I2S1_OUT>, 143 <&clock LCDC0_CLK>, 144 <&clock SCALER_PLL_CLK>, 145 <&clock VIF_PLL_CLK>, 146 <&cru SCLK_I2S1_OUT>, 147 <&clock VIF0_CLK>; 148 #clock-cells = <1>; 149 status = "okay"; 150 }; 151 152 hdmi { 153 compatible = "rockchip,rk618-hdmi"; 154 clocks = <&clock HDMI_CLK>; 155 clock-names = "hdmi"; 156 assigned-clocks = <&clock HDMI_CLK>; 157 assigned-clock-parents = <&clock VIF0_CLK>; 158 interrupt-parent = <&gpio2>; 159 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 160 status = "okay"; 161 162 ports { 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 port@0 { 167 reg = <0>; 168 169 hdmi_in_rgb: endpoint { 170 remote-endpoint = <&rgb_out_hdmi>; 171 }; 172 }; 173 }; 174 }; 175 }; 176}; 177 178&rgb { 179 status = "okay"; 180 181 ports { 182 port@1 { 183 reg = <1>; 184 185 rgb_out_hdmi: endpoint { 186 remote-endpoint = <&hdmi_in_rgb>; 187 }; 188 }; 189 }; 190}; 191 192&rgb_in_vopb { 193 status = "disabled"; 194}; 195 196&rgb_in_vopl { 197 status = "okay"; 198}; 199 200&route_rgb { 201 connect = <&vopl_out_rgb>; 202 status = "disabled"; 203}; 204