1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "px30-robot-no-gpu.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip linux PX30 evb ddr3 board"; 14*4882a593Smuzhiyun compatible = "rockchip,px30-evb-ddr3-v10-linux", "rockchip,px30"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun adc-keys { 17*4882a593Smuzhiyun compatible = "adc-keys"; 18*4882a593Smuzhiyun io-channels = <&saradc 2>; 19*4882a593Smuzhiyun io-channel-names = "buttons"; 20*4882a593Smuzhiyun poll-interval = <100>; 21*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun esc-key { 24*4882a593Smuzhiyun linux,code = <KEY_ESC>; 25*4882a593Smuzhiyun label = "esc"; 26*4882a593Smuzhiyun press-threshold-microvolt = <1310000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun home-key { 30*4882a593Smuzhiyun linux,code = <KEY_HOME>; 31*4882a593Smuzhiyun label = "home"; 32*4882a593Smuzhiyun press-threshold-microvolt = <624000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun menu-key { 36*4882a593Smuzhiyun linux,code = <KEY_MENU>; 37*4882a593Smuzhiyun label = "menu"; 38*4882a593Smuzhiyun press-threshold-microvolt = <987000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun vol-down-key { 42*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 43*4882a593Smuzhiyun label = "volume down"; 44*4882a593Smuzhiyun press-threshold-microvolt = <300000>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vol-up-key { 48*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 49*4882a593Smuzhiyun label = "volume up"; 50*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun rk809-sound { 55*4882a593Smuzhiyun compatible = "simple-audio-card"; 56*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 57*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk809-codec"; 58*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 59*4882a593Smuzhiyun simple-audio-card,cpu { 60*4882a593Smuzhiyun sound-dai = <&i2s1_2ch>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun simple-audio-card,codec { 63*4882a593Smuzhiyun sound-dai = <&rk809_codec>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 68*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 69*4882a593Smuzhiyun /*clocks = <&rk809 1>;*/ 70*4882a593Smuzhiyun /*clock-names = "ext_clock";*/ 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * On the module itself this is one of these (depending 76*4882a593Smuzhiyun * on the actual card populated): 77*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 78*4882a593Smuzhiyun * - PDN (power down when low) 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 84*4882a593Smuzhiyun compatible = "regulator-fixed"; 85*4882a593Smuzhiyun regulator-name = "vcc_phy"; 86*4882a593Smuzhiyun regulator-always-on; 87*4882a593Smuzhiyun regulator-boot-on; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun vcc5v0_sys: vccsys { 91*4882a593Smuzhiyun compatible = "regulator-fixed"; 92*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 93*4882a593Smuzhiyun regulator-always-on; 94*4882a593Smuzhiyun regulator-boot-on; 95*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 96*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun wireless-wlan { 100*4882a593Smuzhiyun compatible = "wlan-platdata"; 101*4882a593Smuzhiyun wifi_chip_type = "AP6210"; 102*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 103*4882a593Smuzhiyun status = "okay"; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun}; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun&bus_apll { 108*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&cpu0 { 113*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&dfi { 117*4882a593Smuzhiyun status = "okay"; 118*4882a593Smuzhiyun}; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun&dmc { 121*4882a593Smuzhiyun center-supply = <&vdd_logic>; 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&emmc { 126*4882a593Smuzhiyun bus-width = <8>; 127*4882a593Smuzhiyun cap-mmc-highspeed; 128*4882a593Smuzhiyun mmc-hs200-1_8v; 129*4882a593Smuzhiyun no-sdio; 130*4882a593Smuzhiyun no-sd; 131*4882a593Smuzhiyun disable-wp; 132*4882a593Smuzhiyun non-removable; 133*4882a593Smuzhiyun num-slots = <1>; 134*4882a593Smuzhiyun status = "okay"; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&gpu { 138*4882a593Smuzhiyun mali-supply = <&vdd_logic>; 139*4882a593Smuzhiyun status = "disabled"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&i2c0 { 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun rk809: pmic@20 { 146*4882a593Smuzhiyun compatible = "rockchip,rk809"; 147*4882a593Smuzhiyun reg = <0x20>; 148*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 149*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 150*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 151*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 152*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 153*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 154*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 155*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 156*4882a593Smuzhiyun rockchip,system-power-controller; 157*4882a593Smuzhiyun wakeup-source; 158*4882a593Smuzhiyun #clock-cells = <1>; 159*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 160*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 161*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 162*4882a593Smuzhiyun pmic-reset-func = <1>; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun vcc1-supply = <&vcc5v0_sys>; 165*4882a593Smuzhiyun vcc2-supply = <&vcc5v0_sys>; 166*4882a593Smuzhiyun vcc3-supply = <&vcc5v0_sys>; 167*4882a593Smuzhiyun vcc4-supply = <&vcc5v0_sys>; 168*4882a593Smuzhiyun vcc5-supply = <&vcc3v3_sys>; 169*4882a593Smuzhiyun vcc6-supply = <&vcc3v3_sys>; 170*4882a593Smuzhiyun vcc7-supply = <&vcc3v3_sys>; 171*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 172*4882a593Smuzhiyun vcc9-supply = <&vcc5v0_sys>; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun pwrkey { 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 179*4882a593Smuzhiyun gpio-controller; 180*4882a593Smuzhiyun #gpio-cells = <2>; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 183*4882a593Smuzhiyun pins = "gpio_slp"; 184*4882a593Smuzhiyun function = "pin_fun0"; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 188*4882a593Smuzhiyun pins = "gpio_slp"; 189*4882a593Smuzhiyun function = "pin_fun1"; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 193*4882a593Smuzhiyun pins = "gpio_slp"; 194*4882a593Smuzhiyun function = "pin_fun2"; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 198*4882a593Smuzhiyun pins = "gpio_slp"; 199*4882a593Smuzhiyun function = "pin_fun3"; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun regulators { 204*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 205*4882a593Smuzhiyun regulator-always-on; 206*4882a593Smuzhiyun regulator-boot-on; 207*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 208*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 209*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 210*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 211*4882a593Smuzhiyun regulator-name = "vdd_logic"; 212*4882a593Smuzhiyun regulator-state-mem { 213*4882a593Smuzhiyun regulator-on-in-suspend; 214*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 219*4882a593Smuzhiyun regulator-always-on; 220*4882a593Smuzhiyun regulator-boot-on; 221*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 222*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 223*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 224*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 225*4882a593Smuzhiyun regulator-name = "vdd_arm"; 226*4882a593Smuzhiyun regulator-state-mem { 227*4882a593Smuzhiyun regulator-off-in-suspend; 228*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 233*4882a593Smuzhiyun regulator-always-on; 234*4882a593Smuzhiyun regulator-boot-on; 235*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 236*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 237*4882a593Smuzhiyun regulator-state-mem { 238*4882a593Smuzhiyun regulator-on-in-suspend; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun vcc_3v0: DCDC_REG4 { 243*4882a593Smuzhiyun regulator-always-on; 244*4882a593Smuzhiyun regulator-boot-on; 245*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 246*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 247*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 248*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 249*4882a593Smuzhiyun regulator-state-mem { 250*4882a593Smuzhiyun regulator-on-in-suspend; 251*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun vcc_1v0: LDO_REG1 { 256*4882a593Smuzhiyun regulator-always-on; 257*4882a593Smuzhiyun regulator-boot-on; 258*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 259*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 260*4882a593Smuzhiyun regulator-name = "vcc_1v0"; 261*4882a593Smuzhiyun regulator-state-mem { 262*4882a593Smuzhiyun regulator-on-in-suspend; 263*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun vcc1v8_soc: LDO_REG2 { 268*4882a593Smuzhiyun regulator-always-on; 269*4882a593Smuzhiyun regulator-boot-on; 270*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 271*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun regulator-name = "vcc1v8_soc"; 274*4882a593Smuzhiyun regulator-state-mem { 275*4882a593Smuzhiyun regulator-on-in-suspend; 276*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun vdd1v0_soc: LDO_REG3 { 281*4882a593Smuzhiyun regulator-always-on; 282*4882a593Smuzhiyun regulator-boot-on; 283*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 284*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun regulator-name = "vcc1v0_soc"; 287*4882a593Smuzhiyun regulator-state-mem { 288*4882a593Smuzhiyun regulator-on-in-suspend; 289*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun vcc3v0_pmu: LDO_REG4 { 294*4882a593Smuzhiyun regulator-always-on; 295*4882a593Smuzhiyun regulator-boot-on; 296*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 297*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun regulator-name = "vcc3v0_pmu"; 300*4882a593Smuzhiyun regulator-state-mem { 301*4882a593Smuzhiyun regulator-on-in-suspend; 302*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 308*4882a593Smuzhiyun regulator-always-on; 309*4882a593Smuzhiyun regulator-boot-on; 310*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 311*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun regulator-name = "vccio_sd"; 314*4882a593Smuzhiyun regulator-state-mem { 315*4882a593Smuzhiyun regulator-on-in-suspend; 316*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun vcc_sd: LDO_REG6 { 321*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 322*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 323*4882a593Smuzhiyun regulator-boot-on; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun regulator-name = "vcc_sd"; 326*4882a593Smuzhiyun regulator-state-mem { 327*4882a593Smuzhiyun regulator-on-in-suspend; 328*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun }; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG7 { 334*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 335*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 338*4882a593Smuzhiyun regulator-state-mem { 339*4882a593Smuzhiyun regulator-off-in-suspend; 340*4882a593Smuzhiyun regulator-suspend-microvolt = <2800000>; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 345*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 346*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 349*4882a593Smuzhiyun regulator-state-mem { 350*4882a593Smuzhiyun regulator-on-in-suspend; 351*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun vdd1v5_dvp: LDO_REG9 { 356*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 357*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun regulator-name = "vdd1v5_dvp"; 360*4882a593Smuzhiyun regulator-state-mem { 361*4882a593Smuzhiyun regulator-off-in-suspend; 362*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun vcc3v3_sys: DCDC_REG5 { 367*4882a593Smuzhiyun regulator-always-on; 368*4882a593Smuzhiyun regulator-boot-on; 369*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 370*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 371*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 372*4882a593Smuzhiyun regulator-state-mem { 373*4882a593Smuzhiyun regulator-on-in-suspend; 374*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 375*4882a593Smuzhiyun }; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun vcc5v0_host: SWITCH_REG1 { 379*4882a593Smuzhiyun regulator-always-on; 380*4882a593Smuzhiyun regulator-boot-on; 381*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun vcc3v3_lcd: SWITCH_REG2 { 385*4882a593Smuzhiyun regulator-boot-on; 386*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd"; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun rk809_codec: codec { 391*4882a593Smuzhiyun #sound-dai-cells = <0>; 392*4882a593Smuzhiyun compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 393*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>; 394*4882a593Smuzhiyun clock-names = "mclk"; 395*4882a593Smuzhiyun pinctrl-names = "default"; 396*4882a593Smuzhiyun pinctrl-0 = <&i2s1_2ch_mclk>; 397*4882a593Smuzhiyun hp-volume = <20>; 398*4882a593Smuzhiyun spk-volume = <3>; 399*4882a593Smuzhiyun status = "okay"; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun}; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun&i2c2 { 405*4882a593Smuzhiyun status = "okay"; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun clock-frequency = <100000>; 408*4882a593Smuzhiyun pinctrl-0 = <&i2c2_xfer>; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun /* These are relatively safe rise/fall times; TODO: measure */ 411*4882a593Smuzhiyun i2c-scl-falling-time-ns = <50>; 412*4882a593Smuzhiyun i2c-scl-rising-time-ns = <300>; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun ov5695: ov5695@36 { 415*4882a593Smuzhiyun compatible = "ovti,ov5695"; 416*4882a593Smuzhiyun reg = <0x36>; 417*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 418*4882a593Smuzhiyun clock-names = "xvclk"; 419*4882a593Smuzhiyun /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 422*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 423*4882a593Smuzhiyun dvdd-supply = <&vdd1v5_dvp>; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 426*4882a593Smuzhiyun pinctrl-names = "default"; 427*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout_m0>; 428*4882a593Smuzhiyun port { 429*4882a593Smuzhiyun ucam_out: endpoint { 430*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam>; 431*4882a593Smuzhiyun data-lanes = <1 2>; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun}; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun&i2s1_2ch { 438*4882a593Smuzhiyun status = "okay"; 439*4882a593Smuzhiyun #sound-dai-cells = <0>; 440*4882a593Smuzhiyun}; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun&io_domains { 443*4882a593Smuzhiyun status = "okay"; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun vccio1-supply = <&vcc_3v0>; 446*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 447*4882a593Smuzhiyun vccio3-supply = <&vcc_3v0>; 448*4882a593Smuzhiyun vccio4-supply = <&vcc3v0_pmu>; 449*4882a593Smuzhiyun vccio5-supply = <&vcc_3v0>; 450*4882a593Smuzhiyun}; 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun&isp_mmu { 453*4882a593Smuzhiyun status = "okay"; 454*4882a593Smuzhiyun}; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun&mipi_dphy_rx0 { 457*4882a593Smuzhiyun status = "okay"; 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun ports { 460*4882a593Smuzhiyun #address-cells = <1>; 461*4882a593Smuzhiyun #size-cells = <0>; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun port@0 { 464*4882a593Smuzhiyun reg = <0>; 465*4882a593Smuzhiyun #address-cells = <1>; 466*4882a593Smuzhiyun #size-cells = <0>; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun mipi_in_ucam: endpoint@1 { 469*4882a593Smuzhiyun reg = <1>; 470*4882a593Smuzhiyun remote-endpoint = <&ucam_out>; 471*4882a593Smuzhiyun data-lanes = <1 2>; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun port@1 { 476*4882a593Smuzhiyun reg = <1>; 477*4882a593Smuzhiyun #address-cells = <1>; 478*4882a593Smuzhiyun #size-cells = <0>; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun dphy_rx0_out: endpoint@0 { 481*4882a593Smuzhiyun reg = <0>; 482*4882a593Smuzhiyun remote-endpoint = <&isp0_mipi_in>; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun }; 486*4882a593Smuzhiyun}; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun&nandc0 { 489*4882a593Smuzhiyun status = "okay"; 490*4882a593Smuzhiyun}; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun&pmu_io_domains { 493*4882a593Smuzhiyun status = "okay"; 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun pmuio1-supply = <&vcc3v0_pmu>; 496*4882a593Smuzhiyun pmuio2-supply = <&vcc3v0_pmu>; 497*4882a593Smuzhiyun}; 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun&rk_rga { 500*4882a593Smuzhiyun status = "okay"; 501*4882a593Smuzhiyun}; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun&rkisp1 { 504*4882a593Smuzhiyun status = "okay"; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun port { 507*4882a593Smuzhiyun #address-cells = <1>; 508*4882a593Smuzhiyun #size-cells = <0>; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun isp0_mipi_in: endpoint@0 { 511*4882a593Smuzhiyun reg = <0>; 512*4882a593Smuzhiyun remote-endpoint = <&dphy_rx0_out>; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun}; 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun&saradc { 518*4882a593Smuzhiyun status = "okay"; 519*4882a593Smuzhiyun vref-supply = <&vcc1v8_soc>; 520*4882a593Smuzhiyun}; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun&sdmmc { 523*4882a593Smuzhiyun bus-width = <4>; 524*4882a593Smuzhiyun cap-mmc-highspeed; 525*4882a593Smuzhiyun cap-sd-highspeed; 526*4882a593Smuzhiyun no-sdio; 527*4882a593Smuzhiyun no-mmc; 528*4882a593Smuzhiyun card-detect-delay = <800>; 529*4882a593Smuzhiyun ignore-pm-notify; 530*4882a593Smuzhiyun /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ 531*4882a593Smuzhiyun sd-uhs-sdr12; 532*4882a593Smuzhiyun sd-uhs-sdr25; 533*4882a593Smuzhiyun sd-uhs-sdr50; 534*4882a593Smuzhiyun sd-uhs-sdr104; 535*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 536*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 537*4882a593Smuzhiyun status = "disabled"; 538*4882a593Smuzhiyun}; 539*4882a593Smuzhiyun 540*4882a593Smuzhiyun&sdio { 541*4882a593Smuzhiyun bus-width = <4>; 542*4882a593Smuzhiyun cap-sd-highspeed; 543*4882a593Smuzhiyun no-sd; 544*4882a593Smuzhiyun no-mmc; 545*4882a593Smuzhiyun ignore-pm-notify; 546*4882a593Smuzhiyun keep-power-in-suspend; 547*4882a593Smuzhiyun non-removable; 548*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 549*4882a593Smuzhiyun sd-uhs-sdr104; 550*4882a593Smuzhiyun status = "okay"; 551*4882a593Smuzhiyun}; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun&mpp_srv { 554*4882a593Smuzhiyun status = "okay"; 555*4882a593Smuzhiyun}; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun&vdpu { 558*4882a593Smuzhiyun status = "okay"; 559*4882a593Smuzhiyun}; 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun&vepu { 562*4882a593Smuzhiyun status = "okay"; 563*4882a593Smuzhiyun}; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun&vpu_mmu { 566*4882a593Smuzhiyun status = "okay"; 567*4882a593Smuzhiyun}; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun&hevc { 570*4882a593Smuzhiyun status = "okay"; 571*4882a593Smuzhiyun}; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun&hevc_mmu { 574*4882a593Smuzhiyun status = "okay"; 575*4882a593Smuzhiyun}; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun&uart1 { 578*4882a593Smuzhiyun pinctrl-names = "default"; 579*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer &uart1_cts>; 580*4882a593Smuzhiyun status = "okay"; 581*4882a593Smuzhiyun}; 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun&u2phy { 584*4882a593Smuzhiyun status = "okay"; 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun u2phy_otg: otg-port { 587*4882a593Smuzhiyun status = "okay"; 588*4882a593Smuzhiyun }; 589*4882a593Smuzhiyun}; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun&usb20_otg { 592*4882a593Smuzhiyun status = "okay"; 593*4882a593Smuzhiyun}; 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun&pinctrl { 596*4882a593Smuzhiyun pmic { 597*4882a593Smuzhiyun pmic_int: pmic_int { 598*4882a593Smuzhiyun rockchip,pins = 599*4882a593Smuzhiyun <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 603*4882a593Smuzhiyun rockchip,pins = 604*4882a593Smuzhiyun <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 605*4882a593Smuzhiyun }; 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 608*4882a593Smuzhiyun rockchip,pins = 609*4882a593Smuzhiyun <0 RK_PA4 1 &pcfg_pull_none>; 610*4882a593Smuzhiyun }; 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 613*4882a593Smuzhiyun rockchip,pins = 614*4882a593Smuzhiyun <0 RK_PA4 2 &pcfg_pull_none>; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun }; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun sdio-pwrseq { 619*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 620*4882a593Smuzhiyun rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 621*4882a593Smuzhiyun }; 622*4882a593Smuzhiyun }; 623*4882a593Smuzhiyun}; 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 626*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 627*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 628