1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the R-Car Gen3 ULCB board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Renesas Electronics Corp. 6*4882a593Smuzhiyun * Copyright (C) 2016 Cogent Embedded, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/* 10*4882a593Smuzhiyun * SSI-AK4613 11*4882a593Smuzhiyun * aplay -D plughw:0,0 xxx.wav 12*4882a593Smuzhiyun * arecord -D plughw:0,0 xxx.wav 13*4882a593Smuzhiyun * SSI-HDMI 14*4882a593Smuzhiyun * aplay -D plughw:0,1 xxx.wav 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 18*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun/ { 21*4882a593Smuzhiyun model = "Renesas R-Car Gen3 ULCB board"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun aliases { 24*4882a593Smuzhiyun serial0 = &scif2; 25*4882a593Smuzhiyun ethernet0 = &avb; 26*4882a593Smuzhiyun mmc0 = &sdhi2; 27*4882a593Smuzhiyun mmc1 = &sdhi0; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun chosen { 31*4882a593Smuzhiyun bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 32*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun audio_clkout: audio-clkout { 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * This is same as <&rcar_sound 0> 38*4882a593Smuzhiyun * but needed to avoid cs2000/rcar_sound probe dead-lock 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun compatible = "fixed-clock"; 41*4882a593Smuzhiyun #clock-cells = <0>; 42*4882a593Smuzhiyun clock-frequency = <12288000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun hdmi0-out { 46*4882a593Smuzhiyun compatible = "hdmi-connector"; 47*4882a593Smuzhiyun type = "a"; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun port { 50*4882a593Smuzhiyun hdmi0_con: endpoint { 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun keyboard { 56*4882a593Smuzhiyun compatible = "gpio-keys"; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun key-1 { 59*4882a593Smuzhiyun linux,code = <KEY_1>; 60*4882a593Smuzhiyun label = "SW3"; 61*4882a593Smuzhiyun wakeup-source; 62*4882a593Smuzhiyun debounce-interval = <20>; 63*4882a593Smuzhiyun gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun leds { 68*4882a593Smuzhiyun compatible = "gpio-leds"; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun led5 { 71*4882a593Smuzhiyun gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun led6 { 74*4882a593Smuzhiyun gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun reg_1p8v: regulator0 { 79*4882a593Smuzhiyun compatible = "regulator-fixed"; 80*4882a593Smuzhiyun regulator-name = "fixed-1.8V"; 81*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 82*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 83*4882a593Smuzhiyun regulator-boot-on; 84*4882a593Smuzhiyun regulator-always-on; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun reg_3p3v: regulator1 { 88*4882a593Smuzhiyun compatible = "regulator-fixed"; 89*4882a593Smuzhiyun regulator-name = "fixed-3.3V"; 90*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 91*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 92*4882a593Smuzhiyun regulator-boot-on; 93*4882a593Smuzhiyun regulator-always-on; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun sound_card: sound { 97*4882a593Smuzhiyun compatible = "audio-graph-card"; 98*4882a593Smuzhiyun label = "rcar-sound"; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun dais = <&rsnd_port0 /* ak4613 */ 101*4882a593Smuzhiyun &rsnd_port1 /* HDMI0 */ 102*4882a593Smuzhiyun >; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun vcc_sdhi0: regulator-vcc-sdhi0 { 106*4882a593Smuzhiyun compatible = "regulator-fixed"; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun regulator-name = "SDHI0 Vcc"; 109*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 110*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; 113*4882a593Smuzhiyun enable-active-high; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun vccq_sdhi0: regulator-vccq-sdhi0 { 117*4882a593Smuzhiyun compatible = "regulator-gpio"; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun regulator-name = "SDHI0 VccQ"; 120*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 121*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 124*4882a593Smuzhiyun gpios-states = <1>; 125*4882a593Smuzhiyun states = <3300000 1>, <1800000 0>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun x12_clk: x12 { 129*4882a593Smuzhiyun compatible = "fixed-clock"; 130*4882a593Smuzhiyun #clock-cells = <0>; 131*4882a593Smuzhiyun clock-frequency = <24576000>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun x23_clk: x23-clock { 135*4882a593Smuzhiyun compatible = "fixed-clock"; 136*4882a593Smuzhiyun #clock-cells = <0>; 137*4882a593Smuzhiyun clock-frequency = <25000000>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun&audio_clk_a { 142*4882a593Smuzhiyun clock-frequency = <22579200>; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&avb { 146*4882a593Smuzhiyun pinctrl-0 = <&avb_pins>; 147*4882a593Smuzhiyun pinctrl-names = "default"; 148*4882a593Smuzhiyun phy-handle = <&phy0>; 149*4882a593Smuzhiyun phy-mode = "rgmii-txid"; 150*4882a593Smuzhiyun status = "okay"; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun phy0: ethernet-phy@0 { 153*4882a593Smuzhiyun rxc-skew-ps = <1500>; 154*4882a593Smuzhiyun reg = <0>; 155*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 156*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 157*4882a593Smuzhiyun reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun}; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun&du { 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun}; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun&ehci1 { 166*4882a593Smuzhiyun status = "okay"; 167*4882a593Smuzhiyun}; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun&extal_clk { 170*4882a593Smuzhiyun clock-frequency = <16666666>; 171*4882a593Smuzhiyun}; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun&extalr_clk { 174*4882a593Smuzhiyun clock-frequency = <32768>; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun&hdmi0 { 178*4882a593Smuzhiyun status = "okay"; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun ports { 181*4882a593Smuzhiyun port@1 { 182*4882a593Smuzhiyun reg = <1>; 183*4882a593Smuzhiyun rcar_dw_hdmi0_out: endpoint { 184*4882a593Smuzhiyun remote-endpoint = <&hdmi0_con>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun port@2 { 188*4882a593Smuzhiyun reg = <2>; 189*4882a593Smuzhiyun dw_hdmi0_snd_in: endpoint { 190*4882a593Smuzhiyun remote-endpoint = <&rsnd_for_hdmi>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&hdmi0_con { 197*4882a593Smuzhiyun remote-endpoint = <&rcar_dw_hdmi0_out>; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&i2c2 { 201*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 202*4882a593Smuzhiyun pinctrl-names = "default"; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun status = "okay"; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun clock-frequency = <100000>; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun ak4613: codec@10 { 209*4882a593Smuzhiyun compatible = "asahi-kasei,ak4613"; 210*4882a593Smuzhiyun #sound-dai-cells = <0>; 211*4882a593Smuzhiyun reg = <0x10>; 212*4882a593Smuzhiyun clocks = <&rcar_sound 3>; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun asahi-kasei,in1-single-end; 215*4882a593Smuzhiyun asahi-kasei,in2-single-end; 216*4882a593Smuzhiyun asahi-kasei,out1-single-end; 217*4882a593Smuzhiyun asahi-kasei,out2-single-end; 218*4882a593Smuzhiyun asahi-kasei,out3-single-end; 219*4882a593Smuzhiyun asahi-kasei,out4-single-end; 220*4882a593Smuzhiyun asahi-kasei,out5-single-end; 221*4882a593Smuzhiyun asahi-kasei,out6-single-end; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun port { 224*4882a593Smuzhiyun ak4613_endpoint: endpoint { 225*4882a593Smuzhiyun remote-endpoint = <&rsnd_for_ak4613>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun cs2000: clk-multiplier@4f { 231*4882a593Smuzhiyun #clock-cells = <0>; 232*4882a593Smuzhiyun compatible = "cirrus,cs2000-cp"; 233*4882a593Smuzhiyun reg = <0x4f>; 234*4882a593Smuzhiyun clocks = <&audio_clkout>, <&x12_clk>; 235*4882a593Smuzhiyun clock-names = "clk_in", "ref_clk"; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun assigned-clocks = <&cs2000>; 238*4882a593Smuzhiyun assigned-clock-rates = <24576000>; /* 1/1 divide */ 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&i2c4 { 243*4882a593Smuzhiyun status = "okay"; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun clock-frequency = <400000>; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun versaclock5: clock-generator@6a { 248*4882a593Smuzhiyun compatible = "idt,5p49v5925"; 249*4882a593Smuzhiyun reg = <0x6a>; 250*4882a593Smuzhiyun #clock-cells = <1>; 251*4882a593Smuzhiyun clocks = <&x23_clk>; 252*4882a593Smuzhiyun clock-names = "xin"; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun}; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun&i2c_dvfs { 257*4882a593Smuzhiyun status = "okay"; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun clock-frequency = <400000>; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun pmic: pmic@30 { 262*4882a593Smuzhiyun pinctrl-0 = <&irq0_pins>; 263*4882a593Smuzhiyun pinctrl-names = "default"; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun compatible = "rohm,bd9571mwv"; 266*4882a593Smuzhiyun reg = <0x30>; 267*4882a593Smuzhiyun interrupt-parent = <&intc_ex>; 268*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 269*4882a593Smuzhiyun interrupt-controller; 270*4882a593Smuzhiyun #interrupt-cells = <2>; 271*4882a593Smuzhiyun gpio-controller; 272*4882a593Smuzhiyun #gpio-cells = <2>; 273*4882a593Smuzhiyun rohm,ddr-backup-power = <0xf>; 274*4882a593Smuzhiyun rohm,rstbmode-pulse; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun regulators { 277*4882a593Smuzhiyun dvfs: dvfs { 278*4882a593Smuzhiyun regulator-name = "dvfs"; 279*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 280*4882a593Smuzhiyun regulator-max-microvolt = <1030000>; 281*4882a593Smuzhiyun regulator-boot-on; 282*4882a593Smuzhiyun regulator-always-on; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun}; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun&ohci1 { 289*4882a593Smuzhiyun status = "okay"; 290*4882a593Smuzhiyun}; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun&pfc { 293*4882a593Smuzhiyun pinctrl-0 = <&scif_clk_pins>; 294*4882a593Smuzhiyun pinctrl-names = "default"; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun avb_pins: avb { 297*4882a593Smuzhiyun mux { 298*4882a593Smuzhiyun groups = "avb_link", "avb_mdio", "avb_mii"; 299*4882a593Smuzhiyun function = "avb"; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun pins_mdio { 303*4882a593Smuzhiyun groups = "avb_mdio"; 304*4882a593Smuzhiyun drive-strength = <24>; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun pins_mii_tx { 308*4882a593Smuzhiyun pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", 309*4882a593Smuzhiyun "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; 310*4882a593Smuzhiyun drive-strength = <12>; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun i2c2_pins: i2c2 { 315*4882a593Smuzhiyun groups = "i2c2_a"; 316*4882a593Smuzhiyun function = "i2c2"; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun irq0_pins: irq0 { 320*4882a593Smuzhiyun groups = "intc_ex_irq0"; 321*4882a593Smuzhiyun function = "intc_ex"; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun scif2_pins: scif2 { 325*4882a593Smuzhiyun groups = "scif2_data_a"; 326*4882a593Smuzhiyun function = "scif2"; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun scif_clk_pins: scif_clk { 330*4882a593Smuzhiyun groups = "scif_clk_a"; 331*4882a593Smuzhiyun function = "scif_clk"; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun sdhi0_pins: sd0 { 335*4882a593Smuzhiyun groups = "sdhi0_data4", "sdhi0_ctrl"; 336*4882a593Smuzhiyun function = "sdhi0"; 337*4882a593Smuzhiyun power-source = <3300>; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun sdhi0_pins_uhs: sd0_uhs { 341*4882a593Smuzhiyun groups = "sdhi0_data4", "sdhi0_ctrl"; 342*4882a593Smuzhiyun function = "sdhi0"; 343*4882a593Smuzhiyun power-source = <1800>; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun sdhi2_pins: sd2 { 347*4882a593Smuzhiyun groups = "sdhi2_data8", "sdhi2_ctrl", "sdhi2_ds"; 348*4882a593Smuzhiyun function = "sdhi2"; 349*4882a593Smuzhiyun power-source = <1800>; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun sound_pins: sound { 353*4882a593Smuzhiyun groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; 354*4882a593Smuzhiyun function = "ssi"; 355*4882a593Smuzhiyun }; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun sound_clk_pins: sound-clk { 358*4882a593Smuzhiyun groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", 359*4882a593Smuzhiyun "audio_clkout_a", "audio_clkout3_a"; 360*4882a593Smuzhiyun function = "audio_clk"; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun usb1_pins: usb1 { 364*4882a593Smuzhiyun groups = "usb1"; 365*4882a593Smuzhiyun function = "usb1"; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun}; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun&rcar_sound { 370*4882a593Smuzhiyun pinctrl-0 = <&sound_pins &sound_clk_pins>; 371*4882a593Smuzhiyun pinctrl-names = "default"; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun /* Single DAI */ 374*4882a593Smuzhiyun #sound-dai-cells = <0>; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun /* audio_clkout0/1/2/3 */ 377*4882a593Smuzhiyun #clock-cells = <1>; 378*4882a593Smuzhiyun clock-frequency = <12288000 11289600>; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun status = "okay"; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun /* update <audio_clk_b> to <cs2000> */ 383*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 1005>, 384*4882a593Smuzhiyun <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 385*4882a593Smuzhiyun <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 386*4882a593Smuzhiyun <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 387*4882a593Smuzhiyun <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 388*4882a593Smuzhiyun <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 389*4882a593Smuzhiyun <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 390*4882a593Smuzhiyun <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 391*4882a593Smuzhiyun <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 392*4882a593Smuzhiyun <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 393*4882a593Smuzhiyun <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 394*4882a593Smuzhiyun <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 395*4882a593Smuzhiyun <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 396*4882a593Smuzhiyun <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 397*4882a593Smuzhiyun <&audio_clk_a>, <&cs2000>, 398*4882a593Smuzhiyun <&audio_clk_c>, 399*4882a593Smuzhiyun <&cpg CPG_CORE CPG_AUDIO_CLK_I>; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun ports { 402*4882a593Smuzhiyun #address-cells = <1>; 403*4882a593Smuzhiyun #size-cells = <0>; 404*4882a593Smuzhiyun rsnd_port0: port@0 { 405*4882a593Smuzhiyun reg = <0>; 406*4882a593Smuzhiyun rsnd_for_ak4613: endpoint { 407*4882a593Smuzhiyun remote-endpoint = <&ak4613_endpoint>; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun dai-format = "left_j"; 410*4882a593Smuzhiyun bitclock-master = <&rsnd_for_ak4613>; 411*4882a593Smuzhiyun frame-master = <&rsnd_for_ak4613>; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun playback = <&ssi0 &src0 &dvc0>; 414*4882a593Smuzhiyun capture = <&ssi1 &src1 &dvc1>; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun rsnd_port1: port@1 { 418*4882a593Smuzhiyun reg = <1>; 419*4882a593Smuzhiyun rsnd_for_hdmi: endpoint { 420*4882a593Smuzhiyun remote-endpoint = <&dw_hdmi0_snd_in>; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun dai-format = "i2s"; 423*4882a593Smuzhiyun bitclock-master = <&rsnd_for_hdmi>; 424*4882a593Smuzhiyun frame-master = <&rsnd_for_hdmi>; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun playback = <&ssi2>; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun}; 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun&rwdt { 433*4882a593Smuzhiyun timeout-sec = <60>; 434*4882a593Smuzhiyun status = "okay"; 435*4882a593Smuzhiyun}; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun&scif2 { 438*4882a593Smuzhiyun pinctrl-0 = <&scif2_pins>; 439*4882a593Smuzhiyun pinctrl-names = "default"; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun status = "okay"; 442*4882a593Smuzhiyun}; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun&scif_clk { 445*4882a593Smuzhiyun clock-frequency = <14745600>; 446*4882a593Smuzhiyun}; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun&sdhi0 { 449*4882a593Smuzhiyun pinctrl-0 = <&sdhi0_pins>; 450*4882a593Smuzhiyun pinctrl-1 = <&sdhi0_pins_uhs>; 451*4882a593Smuzhiyun pinctrl-names = "default", "state_uhs"; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun vmmc-supply = <&vcc_sdhi0>; 454*4882a593Smuzhiyun vqmmc-supply = <&vccq_sdhi0>; 455*4882a593Smuzhiyun cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; 456*4882a593Smuzhiyun bus-width = <4>; 457*4882a593Smuzhiyun sd-uhs-sdr50; 458*4882a593Smuzhiyun sd-uhs-sdr104; 459*4882a593Smuzhiyun status = "okay"; 460*4882a593Smuzhiyun}; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun&sdhi2 { 463*4882a593Smuzhiyun /* used for on-board 8bit eMMC */ 464*4882a593Smuzhiyun pinctrl-0 = <&sdhi2_pins>; 465*4882a593Smuzhiyun pinctrl-1 = <&sdhi2_pins>; 466*4882a593Smuzhiyun pinctrl-names = "default", "state_uhs"; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 469*4882a593Smuzhiyun vqmmc-supply = <®_1p8v>; 470*4882a593Smuzhiyun bus-width = <8>; 471*4882a593Smuzhiyun mmc-hs200-1_8v; 472*4882a593Smuzhiyun mmc-hs400-1_8v; 473*4882a593Smuzhiyun non-removable; 474*4882a593Smuzhiyun full-pwr-cycle-in-suspend; 475*4882a593Smuzhiyun status = "okay"; 476*4882a593Smuzhiyun}; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun&ssi1 { 479*4882a593Smuzhiyun shared-pin; 480*4882a593Smuzhiyun}; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun&usb2_phy1 { 483*4882a593Smuzhiyun pinctrl-0 = <&usb1_pins>; 484*4882a593Smuzhiyun pinctrl-names = "default"; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun status = "okay"; 487*4882a593Smuzhiyun}; 488