xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the Eagle board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016-2017 Renesas Electronics Corp.
6*4882a593Smuzhiyun * Copyright (C) 2017 Cogent Embedded, Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/dts-v1/;
10*4882a593Smuzhiyun#include "r8a77970.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Renesas Eagle board based on r8a77970";
14*4882a593Smuzhiyun	compatible = "renesas,eagle", "renesas,r8a77970";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	aliases {
17*4882a593Smuzhiyun		serial0 = &scif0;
18*4882a593Smuzhiyun		ethernet0 = &avb;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	chosen {
22*4882a593Smuzhiyun		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
23*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	d3p3: regulator-fixed {
27*4882a593Smuzhiyun		compatible = "regulator-fixed";
28*4882a593Smuzhiyun		regulator-name = "fixed-3.3V";
29*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
30*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
31*4882a593Smuzhiyun		regulator-boot-on;
32*4882a593Smuzhiyun		regulator-always-on;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	hdmi-out {
36*4882a593Smuzhiyun		compatible = "hdmi-connector";
37*4882a593Smuzhiyun		type = "a";
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		port {
40*4882a593Smuzhiyun			hdmi_con_out: endpoint {
41*4882a593Smuzhiyun				remote-endpoint = <&adv7511_out>;
42*4882a593Smuzhiyun			};
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	lvds-decoder {
47*4882a593Smuzhiyun		compatible = "thine,thc63lvd1024";
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun		vcc-supply = <&d3p3>;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		ports {
52*4882a593Smuzhiyun			#address-cells = <1>;
53*4882a593Smuzhiyun			#size-cells = <0>;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun			port@0 {
56*4882a593Smuzhiyun				reg = <0>;
57*4882a593Smuzhiyun				thc63lvd1024_in: endpoint {
58*4882a593Smuzhiyun					remote-endpoint = <&lvds0_out>;
59*4882a593Smuzhiyun				};
60*4882a593Smuzhiyun			};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun			port@2 {
63*4882a593Smuzhiyun				reg = <2>;
64*4882a593Smuzhiyun				thc63lvd1024_out: endpoint {
65*4882a593Smuzhiyun					remote-endpoint = <&adv7511_in>;
66*4882a593Smuzhiyun				};
67*4882a593Smuzhiyun			};
68*4882a593Smuzhiyun		};
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	memory@48000000 {
72*4882a593Smuzhiyun		device_type = "memory";
73*4882a593Smuzhiyun		/* first 128MB is reserved for secure area. */
74*4882a593Smuzhiyun		reg = <0x0 0x48000000 0x0 0x38000000>;
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun&avb {
79*4882a593Smuzhiyun	pinctrl-0 = <&avb_pins>;
80*4882a593Smuzhiyun	pinctrl-names = "default";
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	renesas,no-ether-link;
83*4882a593Smuzhiyun	phy-handle = <&phy0>;
84*4882a593Smuzhiyun	phy-mode = "rgmii-id";
85*4882a593Smuzhiyun	status = "okay";
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	phy0: ethernet-phy@0 {
88*4882a593Smuzhiyun		rxc-skew-ps = <1500>;
89*4882a593Smuzhiyun		reg = <0>;
90*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
91*4882a593Smuzhiyun		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
92*4882a593Smuzhiyun	};
93*4882a593Smuzhiyun};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun&canfd {
96*4882a593Smuzhiyun	pinctrl-0 = <&canfd0_pins>;
97*4882a593Smuzhiyun	pinctrl-names = "default";
98*4882a593Smuzhiyun	status = "okay";
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	channel0 {
101*4882a593Smuzhiyun		status = "okay";
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&du {
106*4882a593Smuzhiyun	status = "okay";
107*4882a593Smuzhiyun};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun&extal_clk {
110*4882a593Smuzhiyun	clock-frequency = <16666666>;
111*4882a593Smuzhiyun};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun&extalr_clk {
114*4882a593Smuzhiyun	clock-frequency = <32768>;
115*4882a593Smuzhiyun};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun&i2c0 {
118*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
119*4882a593Smuzhiyun	pinctrl-names = "default";
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	status = "okay";
122*4882a593Smuzhiyun	clock-frequency = <400000>;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	io_expander: gpio@20 {
125*4882a593Smuzhiyun		compatible = "onnn,pca9654";
126*4882a593Smuzhiyun		reg = <0x20>;
127*4882a593Smuzhiyun		gpio-controller;
128*4882a593Smuzhiyun		#gpio-cells = <2>;
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun	hdmi@39 {
132*4882a593Smuzhiyun		compatible = "adi,adv7511w";
133*4882a593Smuzhiyun		reg = <0x39>;
134*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
135*4882a593Smuzhiyun		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		adi,input-depth = <8>;
138*4882a593Smuzhiyun		adi,input-colorspace = "rgb";
139*4882a593Smuzhiyun		adi,input-clock = "1x";
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		ports {
142*4882a593Smuzhiyun			#address-cells = <1>;
143*4882a593Smuzhiyun			#size-cells = <0>;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun			port@0 {
146*4882a593Smuzhiyun				reg = <0>;
147*4882a593Smuzhiyun				adv7511_in: endpoint {
148*4882a593Smuzhiyun					remote-endpoint = <&thc63lvd1024_out>;
149*4882a593Smuzhiyun				};
150*4882a593Smuzhiyun			};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun			port@1 {
153*4882a593Smuzhiyun				reg = <1>;
154*4882a593Smuzhiyun				adv7511_out: endpoint {
155*4882a593Smuzhiyun					remote-endpoint = <&hdmi_con_out>;
156*4882a593Smuzhiyun				};
157*4882a593Smuzhiyun			};
158*4882a593Smuzhiyun		};
159*4882a593Smuzhiyun	};
160*4882a593Smuzhiyun};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun&lvds0 {
163*4882a593Smuzhiyun	status = "okay";
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun	ports {
166*4882a593Smuzhiyun		port@1 {
167*4882a593Smuzhiyun			lvds0_out: endpoint {
168*4882a593Smuzhiyun				remote-endpoint = <&thc63lvd1024_in>;
169*4882a593Smuzhiyun			};
170*4882a593Smuzhiyun		};
171*4882a593Smuzhiyun	};
172*4882a593Smuzhiyun};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun&pfc {
175*4882a593Smuzhiyun	avb_pins: avb0 {
176*4882a593Smuzhiyun		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
177*4882a593Smuzhiyun		function = "avb0";
178*4882a593Smuzhiyun	};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun	canfd0_pins: canfd0 {
181*4882a593Smuzhiyun		groups = "canfd0_data_a";
182*4882a593Smuzhiyun		function = "canfd0";
183*4882a593Smuzhiyun	};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun	i2c0_pins: i2c0 {
186*4882a593Smuzhiyun		groups = "i2c0";
187*4882a593Smuzhiyun		function = "i2c0";
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun	qspi0_pins: qspi0 {
191*4882a593Smuzhiyun		groups = "qspi0_ctrl", "qspi0_data4";
192*4882a593Smuzhiyun		function = "qspi0";
193*4882a593Smuzhiyun	};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	scif0_pins: scif0 {
196*4882a593Smuzhiyun		groups = "scif0_data";
197*4882a593Smuzhiyun		function = "scif0";
198*4882a593Smuzhiyun	};
199*4882a593Smuzhiyun};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun&rpc {
202*4882a593Smuzhiyun	pinctrl-0 = <&qspi0_pins>;
203*4882a593Smuzhiyun	pinctrl-names = "default";
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun	flash@0 {
208*4882a593Smuzhiyun		compatible = "spansion,s25fs512s", "jedec,spi-nor";
209*4882a593Smuzhiyun		reg = <0>;
210*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
211*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun		partitions {
214*4882a593Smuzhiyun			compatible = "fixed-partitions";
215*4882a593Smuzhiyun			#address-cells = <1>;
216*4882a593Smuzhiyun			#size-cells = <1>;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun			bootparam@0 {
219*4882a593Smuzhiyun				reg = <0x00000000 0x040000>;
220*4882a593Smuzhiyun				read-only;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun			cr7@40000 {
223*4882a593Smuzhiyun				reg = <0x00040000 0x080000>;
224*4882a593Smuzhiyun				read-only;
225*4882a593Smuzhiyun			};
226*4882a593Smuzhiyun			cert_header_sa3@c0000 {
227*4882a593Smuzhiyun				reg = <0x000c0000 0x080000>;
228*4882a593Smuzhiyun				read-only;
229*4882a593Smuzhiyun			};
230*4882a593Smuzhiyun			bl2@140000 {
231*4882a593Smuzhiyun				reg = <0x00140000 0x040000>;
232*4882a593Smuzhiyun				read-only;
233*4882a593Smuzhiyun			};
234*4882a593Smuzhiyun			cert_header_sa6@180000 {
235*4882a593Smuzhiyun				reg = <0x00180000 0x040000>;
236*4882a593Smuzhiyun				read-only;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun			bl31@1c0000 {
239*4882a593Smuzhiyun				reg = <0x001c0000 0x460000>;
240*4882a593Smuzhiyun				read-only;
241*4882a593Smuzhiyun			};
242*4882a593Smuzhiyun			uboot@640000 {
243*4882a593Smuzhiyun				reg = <0x00640000 0x0c0000>;
244*4882a593Smuzhiyun				read-only;
245*4882a593Smuzhiyun			};
246*4882a593Smuzhiyun			uboot-env@700000 {
247*4882a593Smuzhiyun				reg = <0x00700000 0x040000>;
248*4882a593Smuzhiyun				read-only;
249*4882a593Smuzhiyun			};
250*4882a593Smuzhiyun			dtb@740000 {
251*4882a593Smuzhiyun				reg = <0x00740000 0x080000>;
252*4882a593Smuzhiyun			};
253*4882a593Smuzhiyun			kernel@7c0000 {
254*4882a593Smuzhiyun				reg = <0x007c0000 0x1400000>;
255*4882a593Smuzhiyun			};
256*4882a593Smuzhiyun			user@1bc0000 {
257*4882a593Smuzhiyun				reg = <0x01bc0000 0x2440000>;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun		};
260*4882a593Smuzhiyun	};
261*4882a593Smuzhiyun};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun&rwdt {
264*4882a593Smuzhiyun	timeout-sec = <60>;
265*4882a593Smuzhiyun	status = "okay";
266*4882a593Smuzhiyun};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun&scif0 {
269*4882a593Smuzhiyun	pinctrl-0 = <&scif0_pins>;
270*4882a593Smuzhiyun	pinctrl-names = "default";
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun	status = "okay";
273*4882a593Smuzhiyun};
274