1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Corp. 6*4882a593Smuzhiyun * Copyright (C) 2018 Cogent Embedded, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "r8a77965.dtsi" 11*4882a593Smuzhiyun#include "ulcb.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Renesas M3NULCB board based on r8a77965"; 15*4882a593Smuzhiyun compatible = "renesas,m3nulcb", "renesas,r8a77965"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun memory@48000000 { 18*4882a593Smuzhiyun device_type = "memory"; 19*4882a593Smuzhiyun /* first 128MB is reserved for secure area. */ 20*4882a593Smuzhiyun reg = <0x0 0x48000000 0x0 0x78000000>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun}; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun&du { 25*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 724>, 26*4882a593Smuzhiyun <&cpg CPG_MOD 723>, 27*4882a593Smuzhiyun <&cpg CPG_MOD 721>, 28*4882a593Smuzhiyun <&versaclock5 1>, 29*4882a593Smuzhiyun <&versaclock5 3>, 30*4882a593Smuzhiyun <&versaclock5 2>; 31*4882a593Smuzhiyun clock-names = "du.0", "du.1", "du.3", 32*4882a593Smuzhiyun "dclkin.0", "dclkin.1", "dclkin.3"; 33*4882a593Smuzhiyun}; 34