1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2019 Renesas Electronics Corp. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun aliases { 10*4882a593Smuzhiyun ethernet0 = &avb; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun chosen { 14*4882a593Smuzhiyun bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&avb { 19*4882a593Smuzhiyun pinctrl-0 = <&avb_pins>; 20*4882a593Smuzhiyun pinctrl-names = "default"; 21*4882a593Smuzhiyun phy-handle = <&phy0>; 22*4882a593Smuzhiyun tx-internal-delay-ps = <2000>; 23*4882a593Smuzhiyun rx-internal-delay-ps = <1800>; 24*4882a593Smuzhiyun status = "okay"; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun phy0: ethernet-phy@0 { 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 29*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 30*4882a593Smuzhiyun reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&can0 { 35*4882a593Smuzhiyun pinctrl-0 = <&can0_pins>; 36*4882a593Smuzhiyun pinctrl-names = "default"; 37*4882a593Smuzhiyun status = "okay"; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&can1 { 41*4882a593Smuzhiyun pinctrl-0 = <&can1_pins>; 42*4882a593Smuzhiyun pinctrl-names = "default"; 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&pciec0 { 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&pfc { 51*4882a593Smuzhiyun pinctrl-0 = <&scif_clk_pins>; 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun avb_pins: avb { 55*4882a593Smuzhiyun mux { 56*4882a593Smuzhiyun groups = "avb_link", "avb_mdio", "avb_mii"; 57*4882a593Smuzhiyun function = "avb"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun pins_mdio { 61*4882a593Smuzhiyun groups = "avb_mdio"; 62*4882a593Smuzhiyun drive-strength = <24>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pins_mii_tx { 66*4882a593Smuzhiyun pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", 67*4882a593Smuzhiyun "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; 68*4882a593Smuzhiyun drive-strength = <12>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun can0_pins: can0 { 73*4882a593Smuzhiyun groups = "can0_data_a"; 74*4882a593Smuzhiyun function = "can0"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun can1_pins: can1 { 78*4882a593Smuzhiyun groups = "can1_data"; 79*4882a593Smuzhiyun function = "can1"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun pwm0_pins: pwm0 { 83*4882a593Smuzhiyun groups = "pwm0"; 84*4882a593Smuzhiyun function = "pwm0"; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&pwm0 { 89*4882a593Smuzhiyun pinctrl-0 = <&pwm0_pins>; 90*4882a593Smuzhiyun pinctrl-names = "default"; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun}; 94