xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/renesas/hihope-rev4.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
4*4882a593Smuzhiyun * HiHope RZ/G2[MN] Rev.3.0/4.0 main board common parts
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2020 Renesas Electronics Corp.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include "hihope-common.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	audio_clkout: audio-clkout {
14*4882a593Smuzhiyun		/*
15*4882a593Smuzhiyun		 * This is same as <&rcar_sound 0>
16*4882a593Smuzhiyun		 * but needed to avoid cs2000/rcar_sound probe dead-lock
17*4882a593Smuzhiyun		 */
18*4882a593Smuzhiyun		compatible = "fixed-clock";
19*4882a593Smuzhiyun		#clock-cells = <0>;
20*4882a593Smuzhiyun		clock-frequency = <12288000>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	wlan_en_reg: regulator-wlan_en {
24*4882a593Smuzhiyun		compatible = "regulator-fixed";
25*4882a593Smuzhiyun		regulator-name = "wlan-en-regulator";
26*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
27*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
28*4882a593Smuzhiyun		startup-delay-us = <70000>;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun		gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
31*4882a593Smuzhiyun		enable-active-high;
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	x1801_clk: x1801-clock {
35*4882a593Smuzhiyun		compatible = "fixed-clock";
36*4882a593Smuzhiyun		#clock-cells = <0>;
37*4882a593Smuzhiyun		clock-frequency = <24576000>;
38*4882a593Smuzhiyun	};
39*4882a593Smuzhiyun};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun&hscif0 {
42*4882a593Smuzhiyun	bluetooth {
43*4882a593Smuzhiyun		compatible = "ti,wl1837-st";
44*4882a593Smuzhiyun		enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun&i2c2 {
49*4882a593Smuzhiyun	pinctrl-0 = <&i2c2_pins>;
50*4882a593Smuzhiyun	pinctrl-names = "default";
51*4882a593Smuzhiyun	status = "okay";
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun	cs2000: clk_multiplier@4f {
54*4882a593Smuzhiyun		#clock-cells = <0>;
55*4882a593Smuzhiyun		compatible = "cirrus,cs2000-cp";
56*4882a593Smuzhiyun		reg = <0x4f>;
57*4882a593Smuzhiyun		clocks = <&audio_clkout>, <&x1801_clk>;
58*4882a593Smuzhiyun		clock-names = "clk_in", "ref_clk";
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		assigned-clocks = <&cs2000>;
61*4882a593Smuzhiyun		assigned-clock-rates = <24576000>; /* 1/1 divide */
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun&pfc {
66*4882a593Smuzhiyun	i2c2_pins: i2c2 {
67*4882a593Smuzhiyun		groups = "i2c2_a";
68*4882a593Smuzhiyun		function = "i2c2";
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	sound_clk_pins: sound_clk {
72*4882a593Smuzhiyun		groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clkout_a";
73*4882a593Smuzhiyun		function = "audio_clk";
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	sound_pins: sound {
77*4882a593Smuzhiyun		groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
78*4882a593Smuzhiyun		function = "ssi";
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun&rcar_sound {
83*4882a593Smuzhiyun	pinctrl-0 = <&sound_pins &sound_clk_pins>;
84*4882a593Smuzhiyun	pinctrl-names = "default";
85*4882a593Smuzhiyun	status = "okay";
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	/* Single DAI */
88*4882a593Smuzhiyun	#sound-dai-cells = <0>;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	/* audio_clkout0/1/2/3 */
91*4882a593Smuzhiyun	#clock-cells = <1>;
92*4882a593Smuzhiyun	clock-frequency = <12288000 11289600>;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	/* update <audio_clk_b> to <cs2000> */
95*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 1005>,
96*4882a593Smuzhiyun		 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
97*4882a593Smuzhiyun		 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
98*4882a593Smuzhiyun		 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
99*4882a593Smuzhiyun		 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
100*4882a593Smuzhiyun		 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
101*4882a593Smuzhiyun		 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
102*4882a593Smuzhiyun		 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
103*4882a593Smuzhiyun		 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
104*4882a593Smuzhiyun		 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
105*4882a593Smuzhiyun		 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
106*4882a593Smuzhiyun		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
107*4882a593Smuzhiyun		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
108*4882a593Smuzhiyun		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
109*4882a593Smuzhiyun		 <&audio_clk_a>, <&cs2000>,
110*4882a593Smuzhiyun		 <&audio_clk_c>,
111*4882a593Smuzhiyun		 <&cpg CPG_CORE CPG_AUDIO_CLK_I>;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun	rsnd_port: port {
114*4882a593Smuzhiyun		rsnd_endpoint: endpoint {
115*4882a593Smuzhiyun			remote-endpoint = <&dw_hdmi0_snd_in>;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun			dai-format = "i2s";
118*4882a593Smuzhiyun			bitclock-master = <&rsnd_endpoint>;
119*4882a593Smuzhiyun			frame-master = <&rsnd_endpoint>;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun			playback = <&ssi2>;
122*4882a593Smuzhiyun		};
123*4882a593Smuzhiyun	};
124*4882a593Smuzhiyun};
125