1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Realtek RTD1296 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017-2019 Andreas Färber 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "rtd129x.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun compatible = "realtek,rtd1296"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpus { 14*4882a593Smuzhiyun #address-cells = <2>; 15*4882a593Smuzhiyun #size-cells = <0>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpu0: cpu@0 { 18*4882a593Smuzhiyun device_type = "cpu"; 19*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 20*4882a593Smuzhiyun reg = <0x0 0x0>; 21*4882a593Smuzhiyun next-level-cache = <&l2>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun cpu1: cpu@1 { 25*4882a593Smuzhiyun device_type = "cpu"; 26*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 27*4882a593Smuzhiyun reg = <0x0 0x1>; 28*4882a593Smuzhiyun next-level-cache = <&l2>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun cpu2: cpu@2 { 32*4882a593Smuzhiyun device_type = "cpu"; 33*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 34*4882a593Smuzhiyun reg = <0x0 0x2>; 35*4882a593Smuzhiyun next-level-cache = <&l2>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun cpu3: cpu@3 { 39*4882a593Smuzhiyun device_type = "cpu"; 40*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 41*4882a593Smuzhiyun reg = <0x0 0x3>; 42*4882a593Smuzhiyun next-level-cache = <&l2>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun l2: l2-cache { 46*4882a593Smuzhiyun compatible = "cache"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun timer { 51*4882a593Smuzhiyun compatible = "arm,armv8-timer"; 52*4882a593Smuzhiyun interrupts = <GIC_PPI 13 53*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 54*4882a593Smuzhiyun <GIC_PPI 14 55*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 56*4882a593Smuzhiyun <GIC_PPI 11 57*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 58*4882a593Smuzhiyun <GIC_PPI 10 59*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&arm_pmu { 64*4882a593Smuzhiyun interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 65*4882a593Smuzhiyun}; 66