xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/sdm845-db845c.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2019, Linaro Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11*4882a593Smuzhiyun#include <dt-bindings/sound/qcom,q6afe.h>
12*4882a593Smuzhiyun#include <dt-bindings/sound/qcom,q6asm.h>
13*4882a593Smuzhiyun#include "sdm845.dtsi"
14*4882a593Smuzhiyun#include "pm8998.dtsi"
15*4882a593Smuzhiyun#include "pmi8998.dtsi"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun/ {
18*4882a593Smuzhiyun	model = "Thundercomm Dragonboard 845c";
19*4882a593Smuzhiyun	compatible = "thundercomm,db845c", "qcom,sdm845";
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	aliases {
22*4882a593Smuzhiyun		serial0 = &uart9;
23*4882a593Smuzhiyun		hsuart0 = &uart6;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	chosen {
27*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	dc12v: dc12v-regulator {
31*4882a593Smuzhiyun		compatible = "regulator-fixed";
32*4882a593Smuzhiyun		regulator-name = "DC12V";
33*4882a593Smuzhiyun		regulator-min-microvolt = <12000000>;
34*4882a593Smuzhiyun		regulator-max-microvolt = <12000000>;
35*4882a593Smuzhiyun		regulator-always-on;
36*4882a593Smuzhiyun	};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun	gpio_keys {
39*4882a593Smuzhiyun		compatible = "gpio-keys";
40*4882a593Smuzhiyun		autorepeat;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun		pinctrl-names = "default";
43*4882a593Smuzhiyun		pinctrl-0 = <&vol_up_pin_a>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		vol-up {
46*4882a593Smuzhiyun			label = "Volume Up";
47*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
48*4882a593Smuzhiyun			gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	leds {
53*4882a593Smuzhiyun		compatible = "gpio-leds";
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun		user4 {
56*4882a593Smuzhiyun			label = "green:user4";
57*4882a593Smuzhiyun			gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>;
58*4882a593Smuzhiyun			linux,default-trigger = "panic-indicator";
59*4882a593Smuzhiyun			default-state = "off";
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		wlan {
63*4882a593Smuzhiyun			label = "yellow:wlan";
64*4882a593Smuzhiyun			gpios = <&pm8998_gpio 9 GPIO_ACTIVE_HIGH>;
65*4882a593Smuzhiyun			linux,default-trigger = "phy0tx";
66*4882a593Smuzhiyun			default-state = "off";
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		bt {
70*4882a593Smuzhiyun			label = "blue:bt";
71*4882a593Smuzhiyun			gpios = <&pm8998_gpio 5 GPIO_ACTIVE_HIGH>;
72*4882a593Smuzhiyun			linux,default-trigger = "bluetooth-power";
73*4882a593Smuzhiyun			default-state = "off";
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun	hdmi-out {
78*4882a593Smuzhiyun		compatible = "hdmi-connector";
79*4882a593Smuzhiyun		type = "a";
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		port {
82*4882a593Smuzhiyun			hdmi_con: endpoint {
83*4882a593Smuzhiyun				remote-endpoint = <&lt9611_out>;
84*4882a593Smuzhiyun			};
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	lt9611_1v8: lt9611-vdd18-regulator {
89*4882a593Smuzhiyun		compatible = "regulator-fixed";
90*4882a593Smuzhiyun		regulator-name = "LT9611_1V8";
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		vin-supply = <&vdc_5v>;
93*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
94*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun		gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
97*4882a593Smuzhiyun		enable-active-high;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	lt9611_3v3: lt9611-3v3 {
101*4882a593Smuzhiyun		compatible = "regulator-fixed";
102*4882a593Smuzhiyun		regulator-name = "LT9611_3V3";
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun		vin-supply = <&vdc_3v3>;
105*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
106*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun		// TODO: make it possible to drive same GPIO from two clients
109*4882a593Smuzhiyun		// gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
110*4882a593Smuzhiyun		// enable-active-high;
111*4882a593Smuzhiyun	};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun	pcie0_1p05v: pcie-0-1p05v-regulator {
114*4882a593Smuzhiyun		compatible = "regulator-fixed";
115*4882a593Smuzhiyun		regulator-name = "PCIE0_1.05V";
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun		vin-supply = <&vbat>;
118*4882a593Smuzhiyun		regulator-min-microvolt = <1050000>;
119*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		// TODO: make it possible to drive same GPIO from two clients
122*4882a593Smuzhiyun		// gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
123*4882a593Smuzhiyun		// enable-active-high;
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun	cam0_dvdd_1v2: reg_cam0_dvdd_1v2 {
127*4882a593Smuzhiyun		compatible = "regulator-fixed";
128*4882a593Smuzhiyun		regulator-name = "CAM0_DVDD_1V2";
129*4882a593Smuzhiyun		regulator-min-microvolt = <1200000>;
130*4882a593Smuzhiyun		regulator-max-microvolt = <1200000>;
131*4882a593Smuzhiyun		enable-active-high;
132*4882a593Smuzhiyun		gpio = <&pm8998_gpio 12 GPIO_ACTIVE_HIGH>;
133*4882a593Smuzhiyun		pinctrl-names = "default";
134*4882a593Smuzhiyun		pinctrl-0 = <&cam0_dvdd_1v2_en_default>;
135*4882a593Smuzhiyun		vin-supply = <&vbat>;
136*4882a593Smuzhiyun	};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	cam0_avdd_2v8: reg_cam0_avdd_2v8 {
139*4882a593Smuzhiyun		compatible = "regulator-fixed";
140*4882a593Smuzhiyun		regulator-name = "CAM0_AVDD_2V8";
141*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
142*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
143*4882a593Smuzhiyun		enable-active-high;
144*4882a593Smuzhiyun		gpio = <&pm8998_gpio 10 GPIO_ACTIVE_HIGH>;
145*4882a593Smuzhiyun		pinctrl-names = "default";
146*4882a593Smuzhiyun		pinctrl-0 = <&cam0_avdd_2v8_en_default>;
147*4882a593Smuzhiyun		vin-supply = <&vbat>;
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	/* This regulator is enabled when the VREG_LVS1A_1P8 trace is enabled */
151*4882a593Smuzhiyun	cam3_avdd_2v8: reg_cam3_avdd_2v8 {
152*4882a593Smuzhiyun		compatible = "regulator-fixed";
153*4882a593Smuzhiyun		regulator-name = "CAM3_AVDD_2V8";
154*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
155*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
156*4882a593Smuzhiyun		regulator-always-on;
157*4882a593Smuzhiyun		vin-supply = <&vbat>;
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	pcie0_3p3v_dual: vldo-3v3-regulator {
161*4882a593Smuzhiyun		compatible = "regulator-fixed";
162*4882a593Smuzhiyun		regulator-name = "VLDO_3V3";
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun		vin-supply = <&vbat>;
165*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
166*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun		gpio = <&tlmm 90 GPIO_ACTIVE_HIGH>;
169*4882a593Smuzhiyun		enable-active-high;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun		pinctrl-names = "default";
172*4882a593Smuzhiyun		pinctrl-0 = <&pcie0_pwren_state>;
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun	v5p0_hdmiout: v5p0-hdmiout-regulator {
176*4882a593Smuzhiyun		compatible = "regulator-fixed";
177*4882a593Smuzhiyun		regulator-name = "V5P0_HDMIOUT";
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun		vin-supply = <&vdc_5v>;
180*4882a593Smuzhiyun		regulator-min-microvolt = <500000>;
181*4882a593Smuzhiyun		regulator-max-microvolt = <500000>;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun		// TODO: make it possible to drive same GPIO from two clients
184*4882a593Smuzhiyun		// gpio = <&tlmm 89 GPIO_ACTIVE_HIGH>;
185*4882a593Smuzhiyun		// enable-active-high;
186*4882a593Smuzhiyun	};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun	vbat: vbat-regulator {
189*4882a593Smuzhiyun		compatible = "regulator-fixed";
190*4882a593Smuzhiyun		regulator-name = "VBAT";
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun		vin-supply = <&dc12v>;
193*4882a593Smuzhiyun		regulator-min-microvolt = <4200000>;
194*4882a593Smuzhiyun		regulator-max-microvolt = <4200000>;
195*4882a593Smuzhiyun		regulator-always-on;
196*4882a593Smuzhiyun	};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun	vbat_som: vbat-som-regulator {
199*4882a593Smuzhiyun		compatible = "regulator-fixed";
200*4882a593Smuzhiyun		regulator-name = "VBAT_SOM";
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun		vin-supply = <&dc12v>;
203*4882a593Smuzhiyun		regulator-min-microvolt = <4200000>;
204*4882a593Smuzhiyun		regulator-max-microvolt = <4200000>;
205*4882a593Smuzhiyun		regulator-always-on;
206*4882a593Smuzhiyun	};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	vdc_3v3: vdc-3v3-regulator {
209*4882a593Smuzhiyun		compatible = "regulator-fixed";
210*4882a593Smuzhiyun		regulator-name = "VDC_3V3";
211*4882a593Smuzhiyun		vin-supply = <&dc12v>;
212*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
213*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
214*4882a593Smuzhiyun		regulator-always-on;
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	vdc_5v: vdc-5v-regulator {
218*4882a593Smuzhiyun		compatible = "regulator-fixed";
219*4882a593Smuzhiyun		regulator-name = "VDC_5V";
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun		vin-supply = <&dc12v>;
222*4882a593Smuzhiyun		regulator-min-microvolt = <500000>;
223*4882a593Smuzhiyun		regulator-max-microvolt = <500000>;
224*4882a593Smuzhiyun		regulator-always-on;
225*4882a593Smuzhiyun	};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun	vreg_s4a_1p8: vreg-s4a-1p8 {
228*4882a593Smuzhiyun		compatible = "regulator-fixed";
229*4882a593Smuzhiyun		regulator-name = "vreg_s4a_1p8";
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
232*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
233*4882a593Smuzhiyun		regulator-always-on;
234*4882a593Smuzhiyun	};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun	vph_pwr: vph-pwr-regulator {
237*4882a593Smuzhiyun		compatible = "regulator-fixed";
238*4882a593Smuzhiyun		regulator-name = "vph_pwr";
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun		vin-supply = <&vbat_som>;
241*4882a593Smuzhiyun	};
242*4882a593Smuzhiyun};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun&adsp_pas {
245*4882a593Smuzhiyun	status = "okay";
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun	firmware-name = "qcom/sdm845/adsp.mdt";
248*4882a593Smuzhiyun};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun&apps_rsc {
251*4882a593Smuzhiyun	pm8998-rpmh-regulators {
252*4882a593Smuzhiyun		compatible = "qcom,pm8998-rpmh-regulators";
253*4882a593Smuzhiyun		qcom,pmic-id = "a";
254*4882a593Smuzhiyun		vdd-s1-supply = <&vph_pwr>;
255*4882a593Smuzhiyun		vdd-s2-supply = <&vph_pwr>;
256*4882a593Smuzhiyun		vdd-s3-supply = <&vph_pwr>;
257*4882a593Smuzhiyun		vdd-s4-supply = <&vph_pwr>;
258*4882a593Smuzhiyun		vdd-s5-supply = <&vph_pwr>;
259*4882a593Smuzhiyun		vdd-s6-supply = <&vph_pwr>;
260*4882a593Smuzhiyun		vdd-s7-supply = <&vph_pwr>;
261*4882a593Smuzhiyun		vdd-s8-supply = <&vph_pwr>;
262*4882a593Smuzhiyun		vdd-s9-supply = <&vph_pwr>;
263*4882a593Smuzhiyun		vdd-s10-supply = <&vph_pwr>;
264*4882a593Smuzhiyun		vdd-s11-supply = <&vph_pwr>;
265*4882a593Smuzhiyun		vdd-s12-supply = <&vph_pwr>;
266*4882a593Smuzhiyun		vdd-s13-supply = <&vph_pwr>;
267*4882a593Smuzhiyun		vdd-l1-l27-supply = <&vreg_s7a_1p025>;
268*4882a593Smuzhiyun		vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
269*4882a593Smuzhiyun		vdd-l3-l11-supply = <&vreg_s7a_1p025>;
270*4882a593Smuzhiyun		vdd-l4-l5-supply = <&vreg_s7a_1p025>;
271*4882a593Smuzhiyun		vdd-l6-supply = <&vph_pwr>;
272*4882a593Smuzhiyun		vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
273*4882a593Smuzhiyun		vdd-l9-supply = <&vreg_bob>;
274*4882a593Smuzhiyun		vdd-l10-l23-l25-supply = <&vreg_bob>;
275*4882a593Smuzhiyun		vdd-l13-l19-l21-supply = <&vreg_bob>;
276*4882a593Smuzhiyun		vdd-l16-l28-supply = <&vreg_bob>;
277*4882a593Smuzhiyun		vdd-l18-l22-supply = <&vreg_bob>;
278*4882a593Smuzhiyun		vdd-l20-l24-supply = <&vreg_bob>;
279*4882a593Smuzhiyun		vdd-l26-supply = <&vreg_s3a_1p35>;
280*4882a593Smuzhiyun		vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun		vreg_s3a_1p35: smps3 {
283*4882a593Smuzhiyun			regulator-min-microvolt = <1352000>;
284*4882a593Smuzhiyun			regulator-max-microvolt = <1352000>;
285*4882a593Smuzhiyun		};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun		vreg_s5a_2p04: smps5 {
288*4882a593Smuzhiyun			regulator-min-microvolt = <1904000>;
289*4882a593Smuzhiyun			regulator-max-microvolt = <2040000>;
290*4882a593Smuzhiyun		};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun		vreg_s7a_1p025: smps7 {
293*4882a593Smuzhiyun			regulator-min-microvolt = <900000>;
294*4882a593Smuzhiyun			regulator-max-microvolt = <1028000>;
295*4882a593Smuzhiyun		};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun		vreg_l1a_0p875: ldo1 {
298*4882a593Smuzhiyun			regulator-min-microvolt = <880000>;
299*4882a593Smuzhiyun			regulator-max-microvolt = <880000>;
300*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
301*4882a593Smuzhiyun		};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun		vreg_l5a_0p8: ldo5 {
304*4882a593Smuzhiyun			regulator-min-microvolt = <800000>;
305*4882a593Smuzhiyun			regulator-max-microvolt = <800000>;
306*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
307*4882a593Smuzhiyun		};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun		vreg_l12a_1p8: ldo12 {
310*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
311*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
312*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
313*4882a593Smuzhiyun		};
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun		vreg_l7a_1p8: ldo7 {
316*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
317*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
318*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
319*4882a593Smuzhiyun		};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun		vreg_l13a_2p95: ldo13 {
322*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
323*4882a593Smuzhiyun			regulator-max-microvolt = <2960000>;
324*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
325*4882a593Smuzhiyun		};
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun		vreg_l17a_1p3: ldo17 {
328*4882a593Smuzhiyun			regulator-min-microvolt = <1304000>;
329*4882a593Smuzhiyun			regulator-max-microvolt = <1304000>;
330*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
331*4882a593Smuzhiyun		};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun		vreg_l20a_2p95: ldo20 {
334*4882a593Smuzhiyun			regulator-min-microvolt = <2960000>;
335*4882a593Smuzhiyun			regulator-max-microvolt = <2968000>;
336*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
337*4882a593Smuzhiyun		};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun		vreg_l21a_2p95: ldo21 {
340*4882a593Smuzhiyun			regulator-min-microvolt = <2960000>;
341*4882a593Smuzhiyun			regulator-max-microvolt = <2968000>;
342*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
343*4882a593Smuzhiyun		};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun		vreg_l24a_3p075: ldo24 {
346*4882a593Smuzhiyun			regulator-min-microvolt = <3088000>;
347*4882a593Smuzhiyun			regulator-max-microvolt = <3088000>;
348*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
349*4882a593Smuzhiyun		};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun		vreg_l25a_3p3: ldo25 {
352*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
353*4882a593Smuzhiyun			regulator-max-microvolt = <3312000>;
354*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
355*4882a593Smuzhiyun		};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun		vreg_l26a_1p2: ldo26 {
358*4882a593Smuzhiyun			regulator-min-microvolt = <1200000>;
359*4882a593Smuzhiyun			regulator-max-microvolt = <1200000>;
360*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
361*4882a593Smuzhiyun		};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun		vreg_lvs1a_1p8: lvs1 {
364*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
365*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
366*4882a593Smuzhiyun			regulator-always-on;
367*4882a593Smuzhiyun		};
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun		vreg_lvs2a_1p8: lvs2 {
370*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
371*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
372*4882a593Smuzhiyun			regulator-always-on;
373*4882a593Smuzhiyun		};
374*4882a593Smuzhiyun	};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun	pmi8998-rpmh-regulators {
377*4882a593Smuzhiyun		compatible = "qcom,pmi8998-rpmh-regulators";
378*4882a593Smuzhiyun		qcom,pmic-id = "b";
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun		vdd-bob-supply = <&vph_pwr>;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun		vreg_bob: bob {
383*4882a593Smuzhiyun			regulator-min-microvolt = <3312000>;
384*4882a593Smuzhiyun			regulator-max-microvolt = <3600000>;
385*4882a593Smuzhiyun			regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
386*4882a593Smuzhiyun			regulator-allow-bypass;
387*4882a593Smuzhiyun		};
388*4882a593Smuzhiyun	};
389*4882a593Smuzhiyun};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun&cdsp_pas {
392*4882a593Smuzhiyun	status = "okay";
393*4882a593Smuzhiyun	firmware-name = "qcom/sdm845/cdsp.mdt";
394*4882a593Smuzhiyun};
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun&dsi0 {
397*4882a593Smuzhiyun	status = "okay";
398*4882a593Smuzhiyun	vdda-supply = <&vreg_l26a_1p2>;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun	ports {
401*4882a593Smuzhiyun		port@1 {
402*4882a593Smuzhiyun			endpoint {
403*4882a593Smuzhiyun				remote-endpoint = <&lt9611_a>;
404*4882a593Smuzhiyun				data-lanes = <0 1 2 3>;
405*4882a593Smuzhiyun			};
406*4882a593Smuzhiyun		};
407*4882a593Smuzhiyun	};
408*4882a593Smuzhiyun};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun&dsi0_phy {
411*4882a593Smuzhiyun	status = "okay";
412*4882a593Smuzhiyun	vdds-supply = <&vreg_l1a_0p875>;
413*4882a593Smuzhiyun};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun&gcc {
416*4882a593Smuzhiyun	protected-clocks = <GCC_QSPI_CORE_CLK>,
417*4882a593Smuzhiyun			   <GCC_QSPI_CORE_CLK_SRC>,
418*4882a593Smuzhiyun			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
419*4882a593Smuzhiyun			   <GCC_LPASS_Q6_AXI_CLK>,
420*4882a593Smuzhiyun			   <GCC_LPASS_SWAY_CLK>;
421*4882a593Smuzhiyun};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun&gpu {
424*4882a593Smuzhiyun	zap-shader {
425*4882a593Smuzhiyun		memory-region = <&gpu_mem>;
426*4882a593Smuzhiyun		firmware-name = "qcom/sdm845/a630_zap.mbn";
427*4882a593Smuzhiyun	};
428*4882a593Smuzhiyun};
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun&i2c10 {
431*4882a593Smuzhiyun	status = "okay";
432*4882a593Smuzhiyun	clock-frequency = <400000>;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun	lt9611_codec: hdmi-bridge@3b {
435*4882a593Smuzhiyun		compatible = "lontium,lt9611";
436*4882a593Smuzhiyun		reg = <0x3b>;
437*4882a593Smuzhiyun		#sound-dai-cells = <1>;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun		interrupts-extended = <&tlmm 84 IRQ_TYPE_EDGE_FALLING>;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun		reset-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun		vdd-supply = <&lt9611_1v8>;
444*4882a593Smuzhiyun		vcc-supply = <&lt9611_3v3>;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun		pinctrl-names = "default";
447*4882a593Smuzhiyun		pinctrl-0 = <&lt9611_irq_pin>, <&dsi_sw_sel>;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun		ports {
450*4882a593Smuzhiyun			#address-cells = <1>;
451*4882a593Smuzhiyun			#size-cells = <0>;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun			port@0 {
454*4882a593Smuzhiyun				reg = <0>;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun				lt9611_a: endpoint {
457*4882a593Smuzhiyun					remote-endpoint = <&dsi0_out>;
458*4882a593Smuzhiyun				};
459*4882a593Smuzhiyun			};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun			port@2 {
462*4882a593Smuzhiyun				reg = <2>;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun				lt9611_out: endpoint {
465*4882a593Smuzhiyun					remote-endpoint = <&hdmi_con>;
466*4882a593Smuzhiyun				};
467*4882a593Smuzhiyun			};
468*4882a593Smuzhiyun		};
469*4882a593Smuzhiyun	};
470*4882a593Smuzhiyun};
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun&i2c11 {
473*4882a593Smuzhiyun	/* On Low speed expansion */
474*4882a593Smuzhiyun	label = "LS-I2C1";
475*4882a593Smuzhiyun	status = "okay";
476*4882a593Smuzhiyun};
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun&i2c14 {
479*4882a593Smuzhiyun	/* On Low speed expansion */
480*4882a593Smuzhiyun	label = "LS-I2C0";
481*4882a593Smuzhiyun	status = "okay";
482*4882a593Smuzhiyun};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun&mdss {
485*4882a593Smuzhiyun	status = "okay";
486*4882a593Smuzhiyun};
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun&mdss_mdp {
489*4882a593Smuzhiyun	status = "okay";
490*4882a593Smuzhiyun};
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun&mss_pil {
493*4882a593Smuzhiyun	status = "okay";
494*4882a593Smuzhiyun	firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
495*4882a593Smuzhiyun};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun&pcie0 {
498*4882a593Smuzhiyun	status = "okay";
499*4882a593Smuzhiyun	perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
500*4882a593Smuzhiyun	enable-gpio = <&tlmm 134 GPIO_ACTIVE_HIGH>;
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun	vddpe-3v3-supply = <&pcie0_3p3v_dual>;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun	pinctrl-names = "default";
505*4882a593Smuzhiyun	pinctrl-0 = <&pcie0_default_state>;
506*4882a593Smuzhiyun};
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun&pcie0_phy {
509*4882a593Smuzhiyun	status = "okay";
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun	vdda-phy-supply = <&vreg_l1a_0p875>;
512*4882a593Smuzhiyun	vdda-pll-supply = <&vreg_l26a_1p2>;
513*4882a593Smuzhiyun};
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun&pcie1 {
516*4882a593Smuzhiyun	status = "okay";
517*4882a593Smuzhiyun	perst-gpio = <&tlmm 102 GPIO_ACTIVE_LOW>;
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun	pinctrl-names = "default";
520*4882a593Smuzhiyun	pinctrl-0 = <&pcie1_default_state>;
521*4882a593Smuzhiyun};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun&pcie1_phy {
524*4882a593Smuzhiyun	status = "okay";
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun	vdda-phy-supply = <&vreg_l1a_0p875>;
527*4882a593Smuzhiyun	vdda-pll-supply = <&vreg_l26a_1p2>;
528*4882a593Smuzhiyun};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun&pm8998_gpio {
531*4882a593Smuzhiyun	gpio-line-names =
532*4882a593Smuzhiyun		"NC",
533*4882a593Smuzhiyun		"NC",
534*4882a593Smuzhiyun		"WLAN_SW_CTRL",
535*4882a593Smuzhiyun		"NC",
536*4882a593Smuzhiyun		"PM_GPIO5_BLUE_BT_LED",
537*4882a593Smuzhiyun		"VOL_UP_N",
538*4882a593Smuzhiyun		"NC",
539*4882a593Smuzhiyun		"ADC_IN1",
540*4882a593Smuzhiyun		"PM_GPIO9_YEL_WIFI_LED",
541*4882a593Smuzhiyun		"CAM0_AVDD_EN",
542*4882a593Smuzhiyun		"NC",
543*4882a593Smuzhiyun		"CAM0_DVDD_EN",
544*4882a593Smuzhiyun		"PM_GPIO13_GREEN_U4_LED",
545*4882a593Smuzhiyun		"DIV_CLK2",
546*4882a593Smuzhiyun		"NC",
547*4882a593Smuzhiyun		"NC",
548*4882a593Smuzhiyun		"NC",
549*4882a593Smuzhiyun		"SMB_STAT",
550*4882a593Smuzhiyun		"NC",
551*4882a593Smuzhiyun		"NC",
552*4882a593Smuzhiyun		"ADC_IN2",
553*4882a593Smuzhiyun		"OPTION1",
554*4882a593Smuzhiyun		"WCSS_PWR_REQ",
555*4882a593Smuzhiyun		"PM845_GPIO24",
556*4882a593Smuzhiyun		"OPTION2",
557*4882a593Smuzhiyun		"PM845_SLB";
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun	cam0_dvdd_1v2_en_default: cam0-dvdd-1v2-en {
560*4882a593Smuzhiyun		pins = "gpio12";
561*4882a593Smuzhiyun		function = "normal";
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun		bias-pull-up;
564*4882a593Smuzhiyun		drive-push-pull;
565*4882a593Smuzhiyun		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
566*4882a593Smuzhiyun	};
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun	cam0_avdd_2v8_en_default: cam0-avdd-2v8-en {
569*4882a593Smuzhiyun		pins = "gpio10";
570*4882a593Smuzhiyun		function = "normal";
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun		bias-pull-up;
573*4882a593Smuzhiyun		drive-push-pull;
574*4882a593Smuzhiyun		qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>;
575*4882a593Smuzhiyun	};
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun	vol_up_pin_a: vol-up-active {
578*4882a593Smuzhiyun		pins = "gpio6";
579*4882a593Smuzhiyun		function = "normal";
580*4882a593Smuzhiyun		input-enable;
581*4882a593Smuzhiyun		bias-pull-up;
582*4882a593Smuzhiyun		qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
583*4882a593Smuzhiyun	};
584*4882a593Smuzhiyun};
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun&pm8998_pon {
587*4882a593Smuzhiyun	resin {
588*4882a593Smuzhiyun		compatible = "qcom,pm8941-resin";
589*4882a593Smuzhiyun		interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
590*4882a593Smuzhiyun		debounce = <15625>;
591*4882a593Smuzhiyun		bias-pull-up;
592*4882a593Smuzhiyun		linux,code = <KEY_VOLUMEDOWN>;
593*4882a593Smuzhiyun	};
594*4882a593Smuzhiyun};
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun/* QUAT I2S Uses 4 I2S SD Lines for audio on LT9611 HDMI Bridge */
597*4882a593Smuzhiyun&q6afedai {
598*4882a593Smuzhiyun	qi2s@22 {
599*4882a593Smuzhiyun		reg = <22>;
600*4882a593Smuzhiyun		qcom,sd-lines = <0 1 2 3>;
601*4882a593Smuzhiyun	};
602*4882a593Smuzhiyun};
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun&q6asmdai {
605*4882a593Smuzhiyun	dai@0 {
606*4882a593Smuzhiyun		reg = <0>;
607*4882a593Smuzhiyun	};
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun	dai@1 {
610*4882a593Smuzhiyun		reg = <1>;
611*4882a593Smuzhiyun	};
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun	dai@2 {
614*4882a593Smuzhiyun		reg = <2>;
615*4882a593Smuzhiyun	};
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun	dai@3 {
618*4882a593Smuzhiyun		reg = <3>;
619*4882a593Smuzhiyun		direction = <2>;
620*4882a593Smuzhiyun		is-compress-dai;
621*4882a593Smuzhiyun	};
622*4882a593Smuzhiyun};
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun&qupv3_id_0 {
625*4882a593Smuzhiyun	status = "okay";
626*4882a593Smuzhiyun};
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun&qupv3_id_1 {
629*4882a593Smuzhiyun	status = "okay";
630*4882a593Smuzhiyun};
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun&sdhc_2 {
633*4882a593Smuzhiyun	status = "okay";
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun	pinctrl-names = "default";
636*4882a593Smuzhiyun	pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun	vmmc-supply = <&vreg_l21a_2p95>;
639*4882a593Smuzhiyun	vqmmc-supply = <&vreg_l13a_2p95>;
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun	bus-width = <4>;
642*4882a593Smuzhiyun	cd-gpios = <&tlmm 126 GPIO_ACTIVE_LOW>;
643*4882a593Smuzhiyun};
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun&sound {
646*4882a593Smuzhiyun	compatible = "qcom,db845c-sndcard";
647*4882a593Smuzhiyun	pinctrl-0 = <&quat_mi2s_active
648*4882a593Smuzhiyun			 &quat_mi2s_sd0_active
649*4882a593Smuzhiyun			 &quat_mi2s_sd1_active
650*4882a593Smuzhiyun			 &quat_mi2s_sd2_active
651*4882a593Smuzhiyun			 &quat_mi2s_sd3_active>;
652*4882a593Smuzhiyun	pinctrl-names = "default";
653*4882a593Smuzhiyun	model = "DB845c";
654*4882a593Smuzhiyun	audio-routing =
655*4882a593Smuzhiyun		"RX_BIAS", "MCLK",
656*4882a593Smuzhiyun		"AMIC1", "MIC BIAS1",
657*4882a593Smuzhiyun		"AMIC2", "MIC BIAS2",
658*4882a593Smuzhiyun		"DMIC0", "MIC BIAS1",
659*4882a593Smuzhiyun		"DMIC1", "MIC BIAS1",
660*4882a593Smuzhiyun		"DMIC2", "MIC BIAS3",
661*4882a593Smuzhiyun		"DMIC3", "MIC BIAS3",
662*4882a593Smuzhiyun		"SpkrLeft IN", "SPK1 OUT",
663*4882a593Smuzhiyun		"SpkrRight IN", "SPK2 OUT",
664*4882a593Smuzhiyun		"MM_DL1",  "MultiMedia1 Playback",
665*4882a593Smuzhiyun		"MM_DL2",  "MultiMedia2 Playback",
666*4882a593Smuzhiyun		"MM_DL4",  "MultiMedia4 Playback",
667*4882a593Smuzhiyun		"MultiMedia3 Capture", "MM_UL3";
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun	mm1-dai-link {
670*4882a593Smuzhiyun		link-name = "MultiMedia1";
671*4882a593Smuzhiyun		cpu {
672*4882a593Smuzhiyun			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA1>;
673*4882a593Smuzhiyun		};
674*4882a593Smuzhiyun	};
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun	mm2-dai-link {
677*4882a593Smuzhiyun		link-name = "MultiMedia2";
678*4882a593Smuzhiyun		cpu {
679*4882a593Smuzhiyun			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA2>;
680*4882a593Smuzhiyun		};
681*4882a593Smuzhiyun	};
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun	mm3-dai-link {
684*4882a593Smuzhiyun		link-name = "MultiMedia3";
685*4882a593Smuzhiyun		cpu {
686*4882a593Smuzhiyun			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA3>;
687*4882a593Smuzhiyun		};
688*4882a593Smuzhiyun	};
689*4882a593Smuzhiyun
690*4882a593Smuzhiyun	mm4-dai-link {
691*4882a593Smuzhiyun		link-name = "MultiMedia4";
692*4882a593Smuzhiyun		cpu {
693*4882a593Smuzhiyun			sound-dai = <&q6asmdai  MSM_FRONTEND_DAI_MULTIMEDIA4>;
694*4882a593Smuzhiyun		};
695*4882a593Smuzhiyun	};
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun	hdmi-dai-link {
698*4882a593Smuzhiyun		link-name = "HDMI Playback";
699*4882a593Smuzhiyun		cpu {
700*4882a593Smuzhiyun			sound-dai = <&q6afedai QUATERNARY_MI2S_RX>;
701*4882a593Smuzhiyun		};
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun		platform {
704*4882a593Smuzhiyun			sound-dai = <&q6routing>;
705*4882a593Smuzhiyun		};
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun		codec {
708*4882a593Smuzhiyun			sound-dai =  <&lt9611_codec 0>;
709*4882a593Smuzhiyun		};
710*4882a593Smuzhiyun	};
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun	slim-dai-link {
713*4882a593Smuzhiyun		link-name = "SLIM Playback";
714*4882a593Smuzhiyun		cpu {
715*4882a593Smuzhiyun			sound-dai = <&q6afedai SLIMBUS_0_RX>;
716*4882a593Smuzhiyun		};
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun		platform {
719*4882a593Smuzhiyun			sound-dai = <&q6routing>;
720*4882a593Smuzhiyun		};
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun		codec {
723*4882a593Smuzhiyun			sound-dai =  <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
724*4882a593Smuzhiyun		};
725*4882a593Smuzhiyun	};
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun	slimcap-dai-link {
728*4882a593Smuzhiyun		link-name = "SLIM Capture";
729*4882a593Smuzhiyun		cpu {
730*4882a593Smuzhiyun			sound-dai = <&q6afedai SLIMBUS_0_TX>;
731*4882a593Smuzhiyun		};
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun		platform {
734*4882a593Smuzhiyun			sound-dai = <&q6routing>;
735*4882a593Smuzhiyun		};
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun		codec {
738*4882a593Smuzhiyun			sound-dai = <&wcd9340 1>;
739*4882a593Smuzhiyun		};
740*4882a593Smuzhiyun	};
741*4882a593Smuzhiyun};
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun&spi2 {
744*4882a593Smuzhiyun	/* On Low speed expansion */
745*4882a593Smuzhiyun	label = "LS-SPI0";
746*4882a593Smuzhiyun	status = "okay";
747*4882a593Smuzhiyun};
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun&tlmm {
750*4882a593Smuzhiyun	cam0_default: cam0_default {
751*4882a593Smuzhiyun		rst {
752*4882a593Smuzhiyun			pins = "gpio9";
753*4882a593Smuzhiyun			function = "gpio";
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun			drive-strength = <16>;
756*4882a593Smuzhiyun			bias-disable;
757*4882a593Smuzhiyun		};
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun		mclk0 {
760*4882a593Smuzhiyun			pins = "gpio13";
761*4882a593Smuzhiyun			function = "cam_mclk";
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun			drive-strength = <16>;
764*4882a593Smuzhiyun			bias-disable;
765*4882a593Smuzhiyun		};
766*4882a593Smuzhiyun	};
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun	cam3_default: cam3_default {
769*4882a593Smuzhiyun		rst {
770*4882a593Smuzhiyun			function = "gpio";
771*4882a593Smuzhiyun			pins = "gpio21";
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun			drive-strength = <16>;
774*4882a593Smuzhiyun			bias-disable;
775*4882a593Smuzhiyun		};
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun		mclk3 {
778*4882a593Smuzhiyun			function = "cam_mclk";
779*4882a593Smuzhiyun			pins = "gpio16";
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun			drive-strength = <16>;
782*4882a593Smuzhiyun			bias-disable;
783*4882a593Smuzhiyun		};
784*4882a593Smuzhiyun	};
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun	dsi_sw_sel: dsi-sw-sel {
787*4882a593Smuzhiyun		pins = "gpio120";
788*4882a593Smuzhiyun		function = "gpio";
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun		drive-strength = <2>;
791*4882a593Smuzhiyun		bias-disable;
792*4882a593Smuzhiyun		output-high;
793*4882a593Smuzhiyun	};
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun	lt9611_irq_pin: lt9611-irq {
796*4882a593Smuzhiyun		pins = "gpio84";
797*4882a593Smuzhiyun		function = "gpio";
798*4882a593Smuzhiyun		bias-disable;
799*4882a593Smuzhiyun	};
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun	pcie0_default_state: pcie0-default {
802*4882a593Smuzhiyun		clkreq {
803*4882a593Smuzhiyun			pins = "gpio36";
804*4882a593Smuzhiyun			function = "pci_e0";
805*4882a593Smuzhiyun			bias-pull-up;
806*4882a593Smuzhiyun		};
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun		reset-n {
809*4882a593Smuzhiyun			pins = "gpio35";
810*4882a593Smuzhiyun			function = "gpio";
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun			drive-strength = <2>;
813*4882a593Smuzhiyun			output-low;
814*4882a593Smuzhiyun			bias-pull-down;
815*4882a593Smuzhiyun		};
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun		wake-n {
818*4882a593Smuzhiyun			pins = "gpio37";
819*4882a593Smuzhiyun			function = "gpio";
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun			drive-strength = <2>;
822*4882a593Smuzhiyun			bias-pull-up;
823*4882a593Smuzhiyun		};
824*4882a593Smuzhiyun	};
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun	pcie0_pwren_state: pcie0-pwren {
827*4882a593Smuzhiyun		pins = "gpio90";
828*4882a593Smuzhiyun		function = "gpio";
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun		drive-strength = <2>;
831*4882a593Smuzhiyun		bias-disable;
832*4882a593Smuzhiyun	};
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun	pcie1_default_state: pcie1-default {
835*4882a593Smuzhiyun		perst-n {
836*4882a593Smuzhiyun			pins = "gpio102";
837*4882a593Smuzhiyun			function = "gpio";
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun			drive-strength = <16>;
840*4882a593Smuzhiyun			bias-disable;
841*4882a593Smuzhiyun		};
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun		clkreq {
844*4882a593Smuzhiyun			pins = "gpio103";
845*4882a593Smuzhiyun			function = "pci_e1";
846*4882a593Smuzhiyun			bias-pull-up;
847*4882a593Smuzhiyun		};
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun		wake-n {
850*4882a593Smuzhiyun			pins = "gpio11";
851*4882a593Smuzhiyun			function = "gpio";
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun			drive-strength = <2>;
854*4882a593Smuzhiyun			bias-pull-up;
855*4882a593Smuzhiyun		};
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun		reset-n {
858*4882a593Smuzhiyun			pins = "gpio75";
859*4882a593Smuzhiyun			function = "gpio";
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun			drive-strength = <16>;
862*4882a593Smuzhiyun			bias-pull-up;
863*4882a593Smuzhiyun			output-high;
864*4882a593Smuzhiyun		};
865*4882a593Smuzhiyun	};
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun	sdc2_default_state: sdc2-default {
868*4882a593Smuzhiyun		clk {
869*4882a593Smuzhiyun			pins = "sdc2_clk";
870*4882a593Smuzhiyun			bias-disable;
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun			/*
873*4882a593Smuzhiyun			 * It seems that mmc_test reports errors if drive
874*4882a593Smuzhiyun			 * strength is not 16 on clk, cmd, and data pins.
875*4882a593Smuzhiyun			 */
876*4882a593Smuzhiyun			drive-strength = <16>;
877*4882a593Smuzhiyun		};
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun		cmd {
880*4882a593Smuzhiyun			pins = "sdc2_cmd";
881*4882a593Smuzhiyun			bias-pull-up;
882*4882a593Smuzhiyun			drive-strength = <10>;
883*4882a593Smuzhiyun		};
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun		data {
886*4882a593Smuzhiyun			pins = "sdc2_data";
887*4882a593Smuzhiyun			bias-pull-up;
888*4882a593Smuzhiyun			drive-strength = <10>;
889*4882a593Smuzhiyun		};
890*4882a593Smuzhiyun	};
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun	sdc2_card_det_n: sd-card-det-n {
893*4882a593Smuzhiyun		pins = "gpio126";
894*4882a593Smuzhiyun		function = "gpio";
895*4882a593Smuzhiyun		bias-pull-up;
896*4882a593Smuzhiyun	};
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun	wcd_intr_default: wcd_intr_default {
899*4882a593Smuzhiyun		pins = <54>;
900*4882a593Smuzhiyun		function = "gpio";
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun		input-enable;
903*4882a593Smuzhiyun		bias-pull-down;
904*4882a593Smuzhiyun		drive-strength = <2>;
905*4882a593Smuzhiyun	};
906*4882a593Smuzhiyun};
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun&uart3 {
909*4882a593Smuzhiyun	label = "LS-UART0";
910*4882a593Smuzhiyun	status = "disabled";
911*4882a593Smuzhiyun};
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun&uart6 {
914*4882a593Smuzhiyun	status = "okay";
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun	bluetooth {
917*4882a593Smuzhiyun		compatible = "qcom,wcn3990-bt";
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun		vddio-supply = <&vreg_s4a_1p8>;
920*4882a593Smuzhiyun		vddxo-supply = <&vreg_l7a_1p8>;
921*4882a593Smuzhiyun		vddrf-supply = <&vreg_l17a_1p3>;
922*4882a593Smuzhiyun		vddch0-supply = <&vreg_l25a_3p3>;
923*4882a593Smuzhiyun		max-speed = <3200000>;
924*4882a593Smuzhiyun	};
925*4882a593Smuzhiyun};
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun&uart9 {
928*4882a593Smuzhiyun	label = "LS-UART1";
929*4882a593Smuzhiyun	status = "okay";
930*4882a593Smuzhiyun};
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun&usb_1 {
933*4882a593Smuzhiyun	status = "okay";
934*4882a593Smuzhiyun};
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun&usb_1_dwc3 {
937*4882a593Smuzhiyun	dr_mode = "peripheral";
938*4882a593Smuzhiyun};
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun&usb_1_hsphy {
941*4882a593Smuzhiyun	status = "okay";
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun	vdd-supply = <&vreg_l1a_0p875>;
944*4882a593Smuzhiyun	vdda-pll-supply = <&vreg_l12a_1p8>;
945*4882a593Smuzhiyun	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun	qcom,imp-res-offset-value = <8>;
948*4882a593Smuzhiyun	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
949*4882a593Smuzhiyun	qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
950*4882a593Smuzhiyun	qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
951*4882a593Smuzhiyun};
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun&usb_1_qmpphy {
954*4882a593Smuzhiyun	status = "okay";
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun	vdda-phy-supply = <&vreg_l26a_1p2>;
957*4882a593Smuzhiyun	vdda-pll-supply = <&vreg_l1a_0p875>;
958*4882a593Smuzhiyun};
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun&usb_2 {
961*4882a593Smuzhiyun	status = "okay";
962*4882a593Smuzhiyun};
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun&usb_2_dwc3 {
965*4882a593Smuzhiyun	dr_mode = "host";
966*4882a593Smuzhiyun};
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun&usb_2_hsphy {
969*4882a593Smuzhiyun	status = "okay";
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun	vdd-supply = <&vreg_l1a_0p875>;
972*4882a593Smuzhiyun	vdda-pll-supply = <&vreg_l12a_1p8>;
973*4882a593Smuzhiyun	vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun	qcom,imp-res-offset-value = <8>;
976*4882a593Smuzhiyun	qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
977*4882a593Smuzhiyun};
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun&usb_2_qmpphy {
980*4882a593Smuzhiyun	status = "okay";
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun	vdda-phy-supply = <&vreg_l26a_1p2>;
983*4882a593Smuzhiyun	vdda-pll-supply = <&vreg_l1a_0p875>;
984*4882a593Smuzhiyun};
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun&ufs_mem_hc {
987*4882a593Smuzhiyun	status = "okay";
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun	reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun	vcc-supply = <&vreg_l20a_2p95>;
992*4882a593Smuzhiyun	vcc-max-microamp = <800000>;
993*4882a593Smuzhiyun};
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun&ufs_mem_phy {
996*4882a593Smuzhiyun	status = "okay";
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun	vdda-phy-supply = <&vreg_l1a_0p875>;
999*4882a593Smuzhiyun	vdda-pll-supply = <&vreg_l26a_1p2>;
1000*4882a593Smuzhiyun};
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun&wcd9340{
1003*4882a593Smuzhiyun	pinctrl-0 = <&wcd_intr_default>;
1004*4882a593Smuzhiyun	pinctrl-names = "default";
1005*4882a593Smuzhiyun	clock-names = "extclk";
1006*4882a593Smuzhiyun	clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
1007*4882a593Smuzhiyun	reset-gpios = <&tlmm 64 0>;
1008*4882a593Smuzhiyun	vdd-buck-supply = <&vreg_s4a_1p8>;
1009*4882a593Smuzhiyun	vdd-buck-sido-supply = <&vreg_s4a_1p8>;
1010*4882a593Smuzhiyun	vdd-tx-supply = <&vreg_s4a_1p8>;
1011*4882a593Smuzhiyun	vdd-rx-supply = <&vreg_s4a_1p8>;
1012*4882a593Smuzhiyun	vdd-io-supply = <&vreg_s4a_1p8>;
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun	swm: swm@c85 {
1015*4882a593Smuzhiyun		left_spkr: wsa8810-left{
1016*4882a593Smuzhiyun			compatible = "sdw10217201000";
1017*4882a593Smuzhiyun			reg = <0 1>;
1018*4882a593Smuzhiyun			powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
1019*4882a593Smuzhiyun			#thermal-sensor-cells = <0>;
1020*4882a593Smuzhiyun			sound-name-prefix = "SpkrLeft";
1021*4882a593Smuzhiyun			#sound-dai-cells = <0>;
1022*4882a593Smuzhiyun		};
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun		right_spkr: wsa8810-right{
1025*4882a593Smuzhiyun			compatible = "sdw10217201000";
1026*4882a593Smuzhiyun			powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
1027*4882a593Smuzhiyun			reg = <0 2>;
1028*4882a593Smuzhiyun			#thermal-sensor-cells = <0>;
1029*4882a593Smuzhiyun			sound-name-prefix = "SpkrRight";
1030*4882a593Smuzhiyun			#sound-dai-cells = <0>;
1031*4882a593Smuzhiyun		};
1032*4882a593Smuzhiyun	};
1033*4882a593Smuzhiyun};
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun&wifi {
1036*4882a593Smuzhiyun	status = "okay";
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun	vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
1039*4882a593Smuzhiyun	vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
1040*4882a593Smuzhiyun	vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
1041*4882a593Smuzhiyun	vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun	qcom,snoc-host-cap-8bit-quirk;
1044*4882a593Smuzhiyun};
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun/* PINCTRL - additions to nodes defined in sdm845.dtsi */
1047*4882a593Smuzhiyun&qup_spi2_default {
1048*4882a593Smuzhiyun	drive-strength = <16>;
1049*4882a593Smuzhiyun};
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun&qup_uart3_default{
1052*4882a593Smuzhiyun	pinmux {
1053*4882a593Smuzhiyun		pins = "gpio41", "gpio42", "gpio43", "gpio44";
1054*4882a593Smuzhiyun		function = "qup3";
1055*4882a593Smuzhiyun	};
1056*4882a593Smuzhiyun};
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun&qup_i2c10_default {
1059*4882a593Smuzhiyun	pinconf {
1060*4882a593Smuzhiyun		pins = "gpio55", "gpio56";
1061*4882a593Smuzhiyun		drive-strength = <2>;
1062*4882a593Smuzhiyun		bias-disable;
1063*4882a593Smuzhiyun	};
1064*4882a593Smuzhiyun};
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun&qup_uart6_default {
1067*4882a593Smuzhiyun	pinmux {
1068*4882a593Smuzhiyun		pins = "gpio45", "gpio46", "gpio47", "gpio48";
1069*4882a593Smuzhiyun		function = "qup6";
1070*4882a593Smuzhiyun	};
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun	cts {
1073*4882a593Smuzhiyun		pins = "gpio45";
1074*4882a593Smuzhiyun		bias-disable;
1075*4882a593Smuzhiyun	};
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun	rts-tx {
1078*4882a593Smuzhiyun		pins = "gpio46", "gpio47";
1079*4882a593Smuzhiyun		drive-strength = <2>;
1080*4882a593Smuzhiyun		bias-disable;
1081*4882a593Smuzhiyun	};
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun	rx {
1084*4882a593Smuzhiyun		pins = "gpio48";
1085*4882a593Smuzhiyun		bias-pull-up;
1086*4882a593Smuzhiyun	};
1087*4882a593Smuzhiyun};
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun&qup_uart9_default {
1090*4882a593Smuzhiyun	pinconf-tx {
1091*4882a593Smuzhiyun		pins = "gpio4";
1092*4882a593Smuzhiyun		drive-strength = <2>;
1093*4882a593Smuzhiyun		bias-disable;
1094*4882a593Smuzhiyun	};
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun	pinconf-rx {
1097*4882a593Smuzhiyun		pins = "gpio5";
1098*4882a593Smuzhiyun		drive-strength = <2>;
1099*4882a593Smuzhiyun		bias-pull-up;
1100*4882a593Smuzhiyun	};
1101*4882a593Smuzhiyun};
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun&pm8998_gpio {
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun};
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun&cci {
1108*4882a593Smuzhiyun	status = "okay";
1109*4882a593Smuzhiyun};
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun&cci_i2c0 {
1112*4882a593Smuzhiyun	camera@10 {
1113*4882a593Smuzhiyun		compatible = "ovti,ov8856";
1114*4882a593Smuzhiyun		reg = <0x10>;
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun		// CAM0_RST_N
1117*4882a593Smuzhiyun		reset-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
1118*4882a593Smuzhiyun		pinctrl-names = "default";
1119*4882a593Smuzhiyun		pinctrl-0 = <&cam0_default>;
1120*4882a593Smuzhiyun		gpios = <&tlmm 13 0>,
1121*4882a593Smuzhiyun			<&tlmm 9 GPIO_ACTIVE_LOW>;
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun		clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
1124*4882a593Smuzhiyun		clock-names = "xvclk";
1125*4882a593Smuzhiyun		clock-frequency = <19200000>;
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun		/* The &vreg_s4a_1p8 trace is powered on as a,
1128*4882a593Smuzhiyun		 * so it is represented by a fixed regulator.
1129*4882a593Smuzhiyun		 *
1130*4882a593Smuzhiyun		 * The 2.8V vdda-supply and 1.2V vddd-supply regulators
1131*4882a593Smuzhiyun		 * both have to be enabled through the power management
1132*4882a593Smuzhiyun		 * gpios.
1133*4882a593Smuzhiyun		 */
1134*4882a593Smuzhiyun		power-domains = <&clock_camcc TITAN_TOP_GDSC>;
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun		dovdd-supply = <&vreg_lvs1a_1p8>;
1137*4882a593Smuzhiyun		avdd-supply = <&cam0_avdd_2v8>;
1138*4882a593Smuzhiyun		dvdd-supply = <&cam0_dvdd_1v2>;
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun		status = "disable";
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun		port {
1143*4882a593Smuzhiyun			ov8856_ep: endpoint {
1144*4882a593Smuzhiyun				clock-lanes = <1>;
1145*4882a593Smuzhiyun				link-frequencies = /bits/ 64
1146*4882a593Smuzhiyun					<360000000 180000000>;
1147*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
1148*4882a593Smuzhiyun//				remote-endpoint = <&csiphy0_ep>;
1149*4882a593Smuzhiyun			};
1150*4882a593Smuzhiyun		};
1151*4882a593Smuzhiyun	};
1152*4882a593Smuzhiyun};
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun&cci_i2c1 {
1155*4882a593Smuzhiyun	camera@60 {
1156*4882a593Smuzhiyun		compatible = "ovti,ov7251";
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun		// I2C address as per ov7251.txt linux documentation
1159*4882a593Smuzhiyun		reg = <0x60>;
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun		// CAM3_RST_N
1162*4882a593Smuzhiyun		enable-gpios = <&tlmm 21 0>;
1163*4882a593Smuzhiyun		pinctrl-names = "default";
1164*4882a593Smuzhiyun		pinctrl-0 = <&cam3_default>;
1165*4882a593Smuzhiyun		gpios = <&tlmm 16 0>,
1166*4882a593Smuzhiyun			<&tlmm 21 0>;
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun		clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
1169*4882a593Smuzhiyun		clock-names = "xclk";
1170*4882a593Smuzhiyun		clock-frequency = <24000000>;
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun		/* The &vreg_s4a_1p8 trace always powered on.
1173*4882a593Smuzhiyun		 *
1174*4882a593Smuzhiyun		 * The 2.8V vdda-supply regulator is enabled when the
1175*4882a593Smuzhiyun		 * vreg_s4a_1p8 trace is pulled high.
1176*4882a593Smuzhiyun		 * It too is represented by a fixed regulator.
1177*4882a593Smuzhiyun		 *
1178*4882a593Smuzhiyun		 * No 1.2V vddd-supply regulator is used.
1179*4882a593Smuzhiyun		 */
1180*4882a593Smuzhiyun		power-domains = <&clock_camcc TITAN_TOP_GDSC>;
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun		vdddo-supply = <&vreg_lvs1a_1p8>;
1183*4882a593Smuzhiyun		vdda-supply = <&cam3_avdd_2v8>;
1184*4882a593Smuzhiyun
1185*4882a593Smuzhiyun		status = "disable";
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun		port {
1188*4882a593Smuzhiyun			ov7251_ep: endpoint {
1189*4882a593Smuzhiyun				clock-lanes = <1>;
1190*4882a593Smuzhiyun				data-lanes = <0 1>;
1191*4882a593Smuzhiyun//				remote-endpoint = <&csiphy3_ep>;
1192*4882a593Smuzhiyun			};
1193*4882a593Smuzhiyun		};
1194*4882a593Smuzhiyun	};
1195*4882a593Smuzhiyun};
1196