1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Google Cheza board device tree source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2018 Google LLC. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "sdm845-cheza.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Google Cheza (rev3+)"; 14*4882a593Smuzhiyun compatible = "google,cheza", "qcom,sdm845"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/* PINCTRL - board-specific pinctrl */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun&tlmm { 20*4882a593Smuzhiyun gpio-line-names = "AP_SPI_FP_MISO", 21*4882a593Smuzhiyun "AP_SPI_FP_MOSI", 22*4882a593Smuzhiyun "AP_SPI_FP_CLK", 23*4882a593Smuzhiyun "AP_SPI_FP_CS_L", 24*4882a593Smuzhiyun "UART_AP_TX_DBG_RX", 25*4882a593Smuzhiyun "UART_DBG_TX_AP_RX", 26*4882a593Smuzhiyun "BRIJ_SUSPEND", 27*4882a593Smuzhiyun "FP_RST_L", 28*4882a593Smuzhiyun "FCAM_EN", 29*4882a593Smuzhiyun "", 30*4882a593Smuzhiyun "EDP_BRIJ_IRQ", 31*4882a593Smuzhiyun "EC_IN_RW_ODL", 32*4882a593Smuzhiyun "", 33*4882a593Smuzhiyun "RCAM_MCLK", 34*4882a593Smuzhiyun "FCAM_MCLK", 35*4882a593Smuzhiyun "", 36*4882a593Smuzhiyun "RCAM_EN", 37*4882a593Smuzhiyun "CCI0_SDA", 38*4882a593Smuzhiyun "CCI0_SCL", 39*4882a593Smuzhiyun "CCI1_SDA", 40*4882a593Smuzhiyun "CCI1_SCL", 41*4882a593Smuzhiyun "FCAM_RST_L", 42*4882a593Smuzhiyun "FPMCU_BOOT0", 43*4882a593Smuzhiyun "PEN_RST_L", 44*4882a593Smuzhiyun "PEN_IRQ_L", 45*4882a593Smuzhiyun "FPMCU_SEL_OD", 46*4882a593Smuzhiyun "RCAM_VSYNC", 47*4882a593Smuzhiyun "ESIM_MISO", 48*4882a593Smuzhiyun "ESIM_MOSI", 49*4882a593Smuzhiyun "ESIM_CLK", 50*4882a593Smuzhiyun "ESIM_CS_L", 51*4882a593Smuzhiyun "AP_PEN_1V8_SDA", 52*4882a593Smuzhiyun "AP_PEN_1V8_SCL", 53*4882a593Smuzhiyun "AP_TS_I2C_SDA", 54*4882a593Smuzhiyun "AP_TS_I2C_SCL", 55*4882a593Smuzhiyun "RCAM_RST_L", 56*4882a593Smuzhiyun "", 57*4882a593Smuzhiyun "AP_EDP_BKLTEN", 58*4882a593Smuzhiyun "AP_BRD_ID0", 59*4882a593Smuzhiyun "BOOT_CONFIG_4", 60*4882a593Smuzhiyun "AMP_IRQ_L", 61*4882a593Smuzhiyun "EDP_BRIJ_I2C_SDA", 62*4882a593Smuzhiyun "EDP_BRIJ_I2C_SCL", 63*4882a593Smuzhiyun "EN_PP3300_DX_EDP", 64*4882a593Smuzhiyun "SD_CD_ODL", 65*4882a593Smuzhiyun "BT_UART_RTS", 66*4882a593Smuzhiyun "BT_UART_CTS", 67*4882a593Smuzhiyun "BT_UART_RXD", 68*4882a593Smuzhiyun "BT_UART_TXD", 69*4882a593Smuzhiyun "AMP_I2C_SDA", 70*4882a593Smuzhiyun "AMP_I2C_SCL", 71*4882a593Smuzhiyun "AP_BRD_ID2", 72*4882a593Smuzhiyun "", 73*4882a593Smuzhiyun "AP_EC_SPI_CLK", 74*4882a593Smuzhiyun "AP_EC_SPI_CS_L", 75*4882a593Smuzhiyun "AP_EC_SPI_MISO", 76*4882a593Smuzhiyun "AP_EC_SPI_MOSI", 77*4882a593Smuzhiyun "FORCED_USB_BOOT", 78*4882a593Smuzhiyun "AMP_BCLK", 79*4882a593Smuzhiyun "AMP_LRCLK", 80*4882a593Smuzhiyun "AMP_DOUT", 81*4882a593Smuzhiyun "AMP_DIN", 82*4882a593Smuzhiyun "AP_BRD_ID1", 83*4882a593Smuzhiyun "PEN_PDCT_L", 84*4882a593Smuzhiyun "HP_MCLK", 85*4882a593Smuzhiyun "HP_BCLK", 86*4882a593Smuzhiyun "HP_LRCLK", 87*4882a593Smuzhiyun "HP_DOUT", 88*4882a593Smuzhiyun "HP_DIN", 89*4882a593Smuzhiyun "", 90*4882a593Smuzhiyun "", 91*4882a593Smuzhiyun "", 92*4882a593Smuzhiyun "", 93*4882a593Smuzhiyun "BT_SLIMBUS_DATA", 94*4882a593Smuzhiyun "BT_SLIMBUS_CLK", 95*4882a593Smuzhiyun "AMP_RESET_L", 96*4882a593Smuzhiyun "", 97*4882a593Smuzhiyun "FCAM_VSYNC", 98*4882a593Smuzhiyun "", 99*4882a593Smuzhiyun "AP_SKU_ID0", 100*4882a593Smuzhiyun "EC_WOV_BCLK", 101*4882a593Smuzhiyun "EC_WOV_LRCLK", 102*4882a593Smuzhiyun "EC_WOV_DOUT", 103*4882a593Smuzhiyun "", 104*4882a593Smuzhiyun "", 105*4882a593Smuzhiyun "AP_H1_SPI_MISO", 106*4882a593Smuzhiyun "AP_H1_SPI_MOSI", 107*4882a593Smuzhiyun "AP_H1_SPI_CLK", 108*4882a593Smuzhiyun "AP_H1_SPI_CS_L", 109*4882a593Smuzhiyun "", 110*4882a593Smuzhiyun "AP_SPI_CS0_L", 111*4882a593Smuzhiyun "AP_SPI_MOSI", 112*4882a593Smuzhiyun "AP_SPI_MISO", 113*4882a593Smuzhiyun "", 114*4882a593Smuzhiyun "", 115*4882a593Smuzhiyun "AP_SPI_CLK", 116*4882a593Smuzhiyun "", 117*4882a593Smuzhiyun "RFFE6_CLK", 118*4882a593Smuzhiyun "RFFE6_DATA", 119*4882a593Smuzhiyun "BOOT_CONFIG_1", 120*4882a593Smuzhiyun "BOOT_CONFIG_2", 121*4882a593Smuzhiyun "BOOT_CONFIG_0", 122*4882a593Smuzhiyun "EDP_BRIJ_EN", 123*4882a593Smuzhiyun "", 124*4882a593Smuzhiyun "USB_HS_TX_EN", 125*4882a593Smuzhiyun "UIM2_DATA", 126*4882a593Smuzhiyun "UIM2_CLK", 127*4882a593Smuzhiyun "UIM2_RST", 128*4882a593Smuzhiyun "UIM2_PRESENT", 129*4882a593Smuzhiyun "UIM1_DATA", 130*4882a593Smuzhiyun "UIM1_CLK", 131*4882a593Smuzhiyun "UIM1_RST", 132*4882a593Smuzhiyun "", 133*4882a593Smuzhiyun "AP_SKU_ID1", 134*4882a593Smuzhiyun "SDM_GRFC_8", 135*4882a593Smuzhiyun "SDM_GRFC_9", 136*4882a593Smuzhiyun "AP_RST_REQ", 137*4882a593Smuzhiyun "HP_IRQ", 138*4882a593Smuzhiyun "TS_RESET_L", 139*4882a593Smuzhiyun "PEN_EJECT_ODL", 140*4882a593Smuzhiyun "HUB_RST_L", 141*4882a593Smuzhiyun "FP_TO_AP_IRQ", 142*4882a593Smuzhiyun "AP_EC_INT_L", 143*4882a593Smuzhiyun "", 144*4882a593Smuzhiyun "", 145*4882a593Smuzhiyun "TS_INT_L", 146*4882a593Smuzhiyun "AP_SUSPEND_L", 147*4882a593Smuzhiyun "SDM_GRFC_3", 148*4882a593Smuzhiyun /* 149*4882a593Smuzhiyun * AP_FLASH_WP_L is crossystem ABI. Rev3 schematics 150*4882a593Smuzhiyun * call it BIOS_FLASH_WP_R_L. 151*4882a593Smuzhiyun */ 152*4882a593Smuzhiyun "AP_FLASH_WP_L", 153*4882a593Smuzhiyun "H1_AP_INT_ODL", 154*4882a593Smuzhiyun "QLINK_REQ", 155*4882a593Smuzhiyun "QLINK_EN", 156*4882a593Smuzhiyun "SDM_GRFC_2", 157*4882a593Smuzhiyun "BOOT_CONFIG_3", 158*4882a593Smuzhiyun "WMSS_RESET_L", 159*4882a593Smuzhiyun "SDM_GRFC_0", 160*4882a593Smuzhiyun "SDM_GRFC_1", 161*4882a593Smuzhiyun "RFFE3_DATA", 162*4882a593Smuzhiyun "RFFE3_CLK", 163*4882a593Smuzhiyun "RFFE4_DATA", 164*4882a593Smuzhiyun "RFFE4_CLK", 165*4882a593Smuzhiyun "RFFE5_DATA", 166*4882a593Smuzhiyun "RFFE5_CLK", 167*4882a593Smuzhiyun "GNSS_EN", 168*4882a593Smuzhiyun "WCI2_LTE_COEX_RXD", 169*4882a593Smuzhiyun "WCI2_LTE_COEX_TXD", 170*4882a593Smuzhiyun "AP_RAM_ID0", 171*4882a593Smuzhiyun "AP_RAM_ID1", 172*4882a593Smuzhiyun "RFFE1_DATA", 173*4882a593Smuzhiyun "RFFE1_CLK"; 174*4882a593Smuzhiyun}; 175