xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun#include "tegra186.dtsi"
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun#include <dt-bindings/mfd/max77620.h>
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/ {
7*4882a593Smuzhiyun	model = "NVIDIA Jetson TX2";
8*4882a593Smuzhiyun	compatible = "nvidia,p3310", "nvidia,tegra186";
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun	aliases {
11*4882a593Smuzhiyun		ethernet0 = "/ethernet@2490000";
12*4882a593Smuzhiyun		i2c0 = "/bpmp/i2c";
13*4882a593Smuzhiyun		i2c1 = "/i2c@3160000";
14*4882a593Smuzhiyun		i2c2 = "/i2c@c240000";
15*4882a593Smuzhiyun		i2c3 = "/i2c@3180000";
16*4882a593Smuzhiyun		i2c4 = "/i2c@3190000";
17*4882a593Smuzhiyun		i2c5 = "/i2c@31c0000";
18*4882a593Smuzhiyun		i2c6 = "/i2c@c250000";
19*4882a593Smuzhiyun		i2c7 = "/i2c@31e0000";
20*4882a593Smuzhiyun		mmc0 = "/mmc@3460000";
21*4882a593Smuzhiyun		mmc1 = "/mmc@3400000";
22*4882a593Smuzhiyun		serial0 = &uarta;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	chosen {
26*4882a593Smuzhiyun		bootargs = "earlycon console=ttyS0,115200n8";
27*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	memory@80000000 {
31*4882a593Smuzhiyun		device_type = "memory";
32*4882a593Smuzhiyun		reg = <0x0 0x80000000 0x2 0x00000000>;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	ethernet@2490000 {
36*4882a593Smuzhiyun		status = "okay";
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
39*4882a593Smuzhiyun					 GPIO_ACTIVE_LOW>;
40*4882a593Smuzhiyun		phy-handle = <&phy>;
41*4882a593Smuzhiyun		phy-mode = "rgmii";
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		mdio {
44*4882a593Smuzhiyun			#address-cells = <1>;
45*4882a593Smuzhiyun			#size-cells = <0>;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun			phy: phy@0 {
48*4882a593Smuzhiyun				compatible = "ethernet-phy-ieee802.3-c22";
49*4882a593Smuzhiyun				reg = <0x0>;
50*4882a593Smuzhiyun				interrupt-parent = <&gpio>;
51*4882a593Smuzhiyun				interrupts = <TEGRA186_MAIN_GPIO(M, 5)
52*4882a593Smuzhiyun					      IRQ_TYPE_LEVEL_LOW>;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun				#phy-cells = <0>;
55*4882a593Smuzhiyun			};
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	memory-controller@2c00000 {
60*4882a593Smuzhiyun		status = "okay";
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	serial@3100000 {
64*4882a593Smuzhiyun		status = "okay";
65*4882a593Smuzhiyun	};
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun	i2c@3160000 {
68*4882a593Smuzhiyun		status = "okay";
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		power-monitor@40 {
71*4882a593Smuzhiyun			compatible = "ti,ina3221";
72*4882a593Smuzhiyun			reg = <0x40>;
73*4882a593Smuzhiyun			#address-cells = <1>;
74*4882a593Smuzhiyun			#size-cells = <0>;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun			channel@0 {
77*4882a593Smuzhiyun				reg = <0x0>;
78*4882a593Smuzhiyun				label = "VDD_SYS_GPU";
79*4882a593Smuzhiyun				shunt-resistor-micro-ohms = <10000>;
80*4882a593Smuzhiyun			};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun			channel@1 {
83*4882a593Smuzhiyun				reg = <0x1>;
84*4882a593Smuzhiyun				label = "VDD_SYS_SOC";
85*4882a593Smuzhiyun				shunt-resistor-micro-ohms = <10000>;
86*4882a593Smuzhiyun			};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun			channel@2 {
89*4882a593Smuzhiyun				reg = <0x2>;
90*4882a593Smuzhiyun				label = "VDD_3V8_WIFI";
91*4882a593Smuzhiyun				shunt-resistor-micro-ohms = <10000>;
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun		power-monitor@41 {
96*4882a593Smuzhiyun			compatible = "ti,ina3221";
97*4882a593Smuzhiyun			reg = <0x41>;
98*4882a593Smuzhiyun			#address-cells = <1>;
99*4882a593Smuzhiyun			#size-cells = <0>;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun			channel@0 {
102*4882a593Smuzhiyun				reg = <0x0>;
103*4882a593Smuzhiyun				label = "VDD_IN";
104*4882a593Smuzhiyun				shunt-resistor-micro-ohms = <5000>;
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun			channel@1 {
108*4882a593Smuzhiyun				reg = <0x1>;
109*4882a593Smuzhiyun				label = "VDD_SYS_CPU";
110*4882a593Smuzhiyun				shunt-resistor-micro-ohms = <10000>;
111*4882a593Smuzhiyun			};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun			channel@2 {
114*4882a593Smuzhiyun				reg = <0x2>;
115*4882a593Smuzhiyun				label = "VDD_5V0_DDR";
116*4882a593Smuzhiyun				shunt-resistor-micro-ohms = <10000>;
117*4882a593Smuzhiyun			};
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	i2c@3180000 {
122*4882a593Smuzhiyun		status = "okay";
123*4882a593Smuzhiyun	};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	ddc: i2c@3190000 {
126*4882a593Smuzhiyun		status = "okay";
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	i2c@31c0000 {
130*4882a593Smuzhiyun		status = "okay";
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun	i2c@31e0000 {
134*4882a593Smuzhiyun		status = "okay";
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	/* SDMMC1 (SD/MMC) */
138*4882a593Smuzhiyun	mmc@3400000 {
139*4882a593Smuzhiyun		cd-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>;
140*4882a593Smuzhiyun		wp-gpios = <&gpio TEGRA186_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun		vqmmc-supply = <&vddio_sdmmc1>;
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun	/* SDMMC3 (SDIO) */
146*4882a593Smuzhiyun	mmc@3440000 {
147*4882a593Smuzhiyun		status = "okay";
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	/* SDMMC4 (eMMC) */
151*4882a593Smuzhiyun	mmc@3460000 {
152*4882a593Smuzhiyun		status = "okay";
153*4882a593Smuzhiyun		bus-width = <8>;
154*4882a593Smuzhiyun		non-removable;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun		vqmmc-supply = <&vdd_1v8_ap>;
157*4882a593Smuzhiyun		vmmc-supply = <&vdd_3v3_sys>;
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	hsp@3c00000 {
161*4882a593Smuzhiyun		status = "okay";
162*4882a593Smuzhiyun	};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun	i2c@c240000 {
165*4882a593Smuzhiyun		status = "okay";
166*4882a593Smuzhiyun	};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun	i2c@c250000 {
169*4882a593Smuzhiyun		status = "okay";
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun		/* module ID EEPROM */
172*4882a593Smuzhiyun		eeprom@50 {
173*4882a593Smuzhiyun			compatible = "atmel,24c02";
174*4882a593Smuzhiyun			reg = <0x50>;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun			label = "module";
177*4882a593Smuzhiyun			vcc-supply = <&vdd_1v8>;
178*4882a593Smuzhiyun			address-width = <8>;
179*4882a593Smuzhiyun			pagesize = <8>;
180*4882a593Smuzhiyun			size = <256>;
181*4882a593Smuzhiyun			read-only;
182*4882a593Smuzhiyun		};
183*4882a593Smuzhiyun	};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun	rtc@c2a0000 {
186*4882a593Smuzhiyun		status = "okay";
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	pmc@c360000 {
190*4882a593Smuzhiyun		nvidia,invert-interrupt;
191*4882a593Smuzhiyun	};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	cpus {
194*4882a593Smuzhiyun		cpu@0 {
195*4882a593Smuzhiyun			enable-method = "psci";
196*4882a593Smuzhiyun		};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun		cpu@1 {
199*4882a593Smuzhiyun			enable-method = "psci";
200*4882a593Smuzhiyun		};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun		cpu@2 {
203*4882a593Smuzhiyun			enable-method = "psci";
204*4882a593Smuzhiyun		};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun		cpu@3 {
207*4882a593Smuzhiyun			enable-method = "psci";
208*4882a593Smuzhiyun		};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun		cpu@4 {
211*4882a593Smuzhiyun			enable-method = "psci";
212*4882a593Smuzhiyun		};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun		cpu@5 {
215*4882a593Smuzhiyun			enable-method = "psci";
216*4882a593Smuzhiyun		};
217*4882a593Smuzhiyun	};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun	bpmp {
220*4882a593Smuzhiyun		i2c {
221*4882a593Smuzhiyun			status = "okay";
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun			pmic: pmic@3c {
224*4882a593Smuzhiyun				compatible = "maxim,max77620";
225*4882a593Smuzhiyun				reg = <0x3c>;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun				interrupt-parent = <&pmc>;
228*4882a593Smuzhiyun				interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
229*4882a593Smuzhiyun				#interrupt-cells = <2>;
230*4882a593Smuzhiyun				interrupt-controller;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun				#gpio-cells = <2>;
233*4882a593Smuzhiyun				gpio-controller;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun				pinctrl-names = "default";
236*4882a593Smuzhiyun				pinctrl-0 = <&max77620_default>;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun				max77620_default: pinmux {
239*4882a593Smuzhiyun					gpio0 {
240*4882a593Smuzhiyun						pins = "gpio0";
241*4882a593Smuzhiyun						function = "gpio";
242*4882a593Smuzhiyun					};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun					gpio1 {
245*4882a593Smuzhiyun						pins = "gpio1";
246*4882a593Smuzhiyun						function = "fps-out";
247*4882a593Smuzhiyun						maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
248*4882a593Smuzhiyun					};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun					gpio2 {
251*4882a593Smuzhiyun						pins = "gpio2";
252*4882a593Smuzhiyun						function = "fps-out";
253*4882a593Smuzhiyun						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
254*4882a593Smuzhiyun					};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun					gpio3 {
257*4882a593Smuzhiyun						pins = "gpio3";
258*4882a593Smuzhiyun						function = "fps-out";
259*4882a593Smuzhiyun						maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
260*4882a593Smuzhiyun					};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun					gpio4 {
263*4882a593Smuzhiyun						pins = "gpio4";
264*4882a593Smuzhiyun						function = "32k-out1";
265*4882a593Smuzhiyun						drive-push-pull = <1>;
266*4882a593Smuzhiyun					};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun					gpio5 {
269*4882a593Smuzhiyun						pins = "gpio5";
270*4882a593Smuzhiyun						function = "gpio";
271*4882a593Smuzhiyun						drive-push-pull = <0>;
272*4882a593Smuzhiyun					};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun					gpio6 {
275*4882a593Smuzhiyun						pins = "gpio6";
276*4882a593Smuzhiyun						function = "gpio";
277*4882a593Smuzhiyun						drive-push-pull = <1>;
278*4882a593Smuzhiyun					};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun					gpio7 {
281*4882a593Smuzhiyun						pins = "gpio7";
282*4882a593Smuzhiyun						function = "gpio";
283*4882a593Smuzhiyun						drive-push-pull = <0>;
284*4882a593Smuzhiyun					};
285*4882a593Smuzhiyun				};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun				fps {
288*4882a593Smuzhiyun					fps0 {
289*4882a593Smuzhiyun						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
290*4882a593Smuzhiyun						maxim,shutdown-fps-time-period-us = <640>;
291*4882a593Smuzhiyun					};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun					fps1 {
294*4882a593Smuzhiyun						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
295*4882a593Smuzhiyun						maxim,shutdown-fps-time-period-us = <640>;
296*4882a593Smuzhiyun					};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun					fps2 {
299*4882a593Smuzhiyun						maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
300*4882a593Smuzhiyun						maxim,shutdown-fps-time-period-us = <640>;
301*4882a593Smuzhiyun					};
302*4882a593Smuzhiyun				};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun				regulators {
305*4882a593Smuzhiyun					in-sd0-supply = <&vdd_5v0_sys>;
306*4882a593Smuzhiyun					in-sd1-supply = <&vdd_5v0_sys>;
307*4882a593Smuzhiyun					in-sd2-supply = <&vdd_5v0_sys>;
308*4882a593Smuzhiyun					in-sd3-supply = <&vdd_5v0_sys>;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun					in-ldo0-1-supply = <&vdd_5v0_sys>;
311*4882a593Smuzhiyun					in-ldo2-supply = <&vdd_5v0_sys>;
312*4882a593Smuzhiyun					in-ldo3-5-supply = <&vdd_5v0_sys>;
313*4882a593Smuzhiyun					in-ldo4-6-supply = <&vdd_1v8>;
314*4882a593Smuzhiyun					in-ldo7-8-supply = <&avdd_dsi_csi>;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun					sd0 {
317*4882a593Smuzhiyun						regulator-name = "VDD_DDR_1V1_PMIC";
318*4882a593Smuzhiyun						regulator-min-microvolt = <1100000>;
319*4882a593Smuzhiyun						regulator-max-microvolt = <1100000>;
320*4882a593Smuzhiyun						regulator-always-on;
321*4882a593Smuzhiyun						regulator-boot-on;
322*4882a593Smuzhiyun					};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun					avdd_dsi_csi: sd1 {
325*4882a593Smuzhiyun						regulator-name = "AVDD_DSI_CSI_1V2";
326*4882a593Smuzhiyun						regulator-min-microvolt = <1200000>;
327*4882a593Smuzhiyun						regulator-max-microvolt = <1200000>;
328*4882a593Smuzhiyun					};
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun					vdd_1v8: sd2 {
331*4882a593Smuzhiyun						regulator-name = "VDD_1V8";
332*4882a593Smuzhiyun						regulator-min-microvolt = <1800000>;
333*4882a593Smuzhiyun						regulator-max-microvolt = <1800000>;
334*4882a593Smuzhiyun					};
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun					vdd_3v3_sys: sd3 {
337*4882a593Smuzhiyun						regulator-name = "VDD_3V3_SYS";
338*4882a593Smuzhiyun						regulator-min-microvolt = <3300000>;
339*4882a593Smuzhiyun						regulator-max-microvolt = <3300000>;
340*4882a593Smuzhiyun					};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun					vdd_1v8_pll: ldo0 {
343*4882a593Smuzhiyun						regulator-name = "VDD_1V8_AP_PLL";
344*4882a593Smuzhiyun						regulator-min-microvolt = <1800000>;
345*4882a593Smuzhiyun						regulator-max-microvolt = <1800000>;
346*4882a593Smuzhiyun					};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun					ldo2 {
349*4882a593Smuzhiyun						regulator-name = "VDDIO_3V3_AOHV";
350*4882a593Smuzhiyun						regulator-min-microvolt = <3300000>;
351*4882a593Smuzhiyun						regulator-max-microvolt = <3300000>;
352*4882a593Smuzhiyun						regulator-always-on;
353*4882a593Smuzhiyun						regulator-boot-on;
354*4882a593Smuzhiyun					};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun					vddio_sdmmc1: ldo3 {
357*4882a593Smuzhiyun						regulator-name = "VDDIO_SDMMC1_AP";
358*4882a593Smuzhiyun						regulator-min-microvolt = <1800000>;
359*4882a593Smuzhiyun						regulator-max-microvolt = <3300000>;
360*4882a593Smuzhiyun					};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun					ldo4 {
363*4882a593Smuzhiyun						regulator-name = "VDD_RTC";
364*4882a593Smuzhiyun						regulator-min-microvolt = <1000000>;
365*4882a593Smuzhiyun						regulator-max-microvolt = <1000000>;
366*4882a593Smuzhiyun					};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun					vddio_sdmmc3: ldo5 {
369*4882a593Smuzhiyun						regulator-name = "VDDIO_SDMMC3_AP";
370*4882a593Smuzhiyun						regulator-min-microvolt = <2800000>;
371*4882a593Smuzhiyun						regulator-max-microvolt = <2800000>;
372*4882a593Smuzhiyun					};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun					vdd_hdmi_1v05: ldo7 {
375*4882a593Smuzhiyun						regulator-name = "VDD_HDMI_1V05";
376*4882a593Smuzhiyun						regulator-min-microvolt = <1050000>;
377*4882a593Smuzhiyun						regulator-max-microvolt = <1050000>;
378*4882a593Smuzhiyun					};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun					vdd_pex: ldo8 {
381*4882a593Smuzhiyun						regulator-name = "VDD_PEX_1V05";
382*4882a593Smuzhiyun						regulator-min-microvolt = <1050000>;
383*4882a593Smuzhiyun						regulator-max-microvolt = <1050000>;
384*4882a593Smuzhiyun					};
385*4882a593Smuzhiyun				};
386*4882a593Smuzhiyun			};
387*4882a593Smuzhiyun		};
388*4882a593Smuzhiyun	};
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun	psci {
391*4882a593Smuzhiyun		compatible = "arm,psci-1.0";
392*4882a593Smuzhiyun		status = "okay";
393*4882a593Smuzhiyun		method = "smc";
394*4882a593Smuzhiyun	};
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun	gnd: regulator@0 {
397*4882a593Smuzhiyun		compatible = "regulator-fixed";
398*4882a593Smuzhiyun		regulator-name = "GND";
399*4882a593Smuzhiyun		regulator-min-microvolt = <0>;
400*4882a593Smuzhiyun		regulator-max-microvolt = <0>;
401*4882a593Smuzhiyun		regulator-always-on;
402*4882a593Smuzhiyun		regulator-boot-on;
403*4882a593Smuzhiyun	};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun	vdd_5v0_sys: regulator@1 {
406*4882a593Smuzhiyun		compatible = "regulator-fixed";
407*4882a593Smuzhiyun		regulator-name = "VDD_5V0_SYS";
408*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
409*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
410*4882a593Smuzhiyun		regulator-always-on;
411*4882a593Smuzhiyun		regulator-boot-on;
412*4882a593Smuzhiyun	};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun	vdd_1v8_ap: regulator@2 {
415*4882a593Smuzhiyun		compatible = "regulator-fixed";
416*4882a593Smuzhiyun		regulator-name = "VDD_1V8_AP";
417*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
418*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun		gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
421*4882a593Smuzhiyun		enable-active-high;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun		vin-supply = <&vdd_1v8>;
424*4882a593Smuzhiyun	};
425*4882a593Smuzhiyun};
426