1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include "sparx5_pcb_common.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Sparx5 PCB125 Reference Board"; 11*4882a593Smuzhiyun compatible = "microchip,sparx5-pcb125", "microchip,sparx5"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory@0 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x00000000 0x00000000 0x10000000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun&gpio { 20*4882a593Smuzhiyun emmc_pins: emmc-pins { 21*4882a593Smuzhiyun /* NB: No "GPIO_35", "GPIO_36", "GPIO_37" 22*4882a593Smuzhiyun * (N/A: CARD_nDETECT, CARD_WP, CARD_LED) 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun pins = "GPIO_34", "GPIO_38", "GPIO_39", 25*4882a593Smuzhiyun "GPIO_40", "GPIO_41", "GPIO_42", 26*4882a593Smuzhiyun "GPIO_43", "GPIO_44", "GPIO_45", 27*4882a593Smuzhiyun "GPIO_46", "GPIO_47"; 28*4882a593Smuzhiyun drive-strength = <3>; 29*4882a593Smuzhiyun function = "emmc"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun&sdhci0 { 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun bus-width = <8>; 36*4882a593Smuzhiyun non-removable; 37*4882a593Smuzhiyun pinctrl-0 = <&emmc_pins>; 38*4882a593Smuzhiyun max-frequency = <8000000>; 39*4882a593Smuzhiyun microchip,clock-delay = <10>; 40*4882a593Smuzhiyun}; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&spi0 { 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun spi@0 { 45*4882a593Smuzhiyun compatible = "spi-mux"; 46*4882a593Smuzhiyun mux-controls = <&mux>; 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <0>; 49*4882a593Smuzhiyun reg = <0>; /* CS0 */ 50*4882a593Smuzhiyun spi-flash@9 { 51*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 52*4882a593Smuzhiyun spi-max-frequency = <8000000>; 53*4882a593Smuzhiyun reg = <0x9>; /* SPI */ 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun spi@1 { 57*4882a593Smuzhiyun compatible = "spi-mux"; 58*4882a593Smuzhiyun mux-controls = <&mux 0>; 59*4882a593Smuzhiyun #address-cells = <1>; 60*4882a593Smuzhiyun #size-cells = <0>; 61*4882a593Smuzhiyun reg = <1>; /* CS1 */ 62*4882a593Smuzhiyun spi-flash@9 { 63*4882a593Smuzhiyun compatible = "spi-nand"; 64*4882a593Smuzhiyun pinctrl-0 = <&cs1_pins>; 65*4882a593Smuzhiyun pinctrl-names = "default"; 66*4882a593Smuzhiyun spi-max-frequency = <8000000>; 67*4882a593Smuzhiyun reg = <0x9>; /* SPI */ 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&i2c1 { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun}; 75