1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun&gpio { 7*4882a593Smuzhiyun cs14_pins: cs14-pins { 8*4882a593Smuzhiyun pins = "GPIO_44"; 9*4882a593Smuzhiyun function = "si"; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun}; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun&spi0 { 14*4882a593Smuzhiyun pinctrl-0 = <&si2_pins>; 15*4882a593Smuzhiyun pinctrl-names = "default"; 16*4882a593Smuzhiyun spi@e { 17*4882a593Smuzhiyun compatible = "spi-mux"; 18*4882a593Smuzhiyun mux-controls = <&mux>; 19*4882a593Smuzhiyun #address-cells = <1>; 20*4882a593Smuzhiyun #size-cells = <0>; 21*4882a593Smuzhiyun reg = <14>; /* CS14 */ 22*4882a593Smuzhiyun spi-flash@6 { 23*4882a593Smuzhiyun compatible = "spi-nand"; 24*4882a593Smuzhiyun pinctrl-0 = <&cs14_pins>; 25*4882a593Smuzhiyun pinctrl-names = "default"; 26*4882a593Smuzhiyun reg = <0x6>; /* SPI2 */ 27*4882a593Smuzhiyun spi-max-frequency = <42000000>; 28*4882a593Smuzhiyun rx-sample-delay-ns = <7>; /* Tune for speed */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun}; 32