1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 7*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 8*4882a593Smuzhiyun#include <dt-bindings/clock/microchip,sparx5.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun compatible = "microchip,sparx5"; 12*4882a593Smuzhiyun interrupt-parent = <&gic>; 13*4882a593Smuzhiyun #address-cells = <2>; 14*4882a593Smuzhiyun #size-cells = <1>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun spi0 = &spi0; 18*4882a593Smuzhiyun serial0 = &uart0; 19*4882a593Smuzhiyun serial1 = &uart1; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun chosen { 23*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun cpus { 27*4882a593Smuzhiyun #address-cells = <2>; 28*4882a593Smuzhiyun #size-cells = <0>; 29*4882a593Smuzhiyun cpu-map { 30*4882a593Smuzhiyun cluster0 { 31*4882a593Smuzhiyun core0 { 32*4882a593Smuzhiyun cpu = <&cpu0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun core1 { 35*4882a593Smuzhiyun cpu = <&cpu1>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun cpu0: cpu@0 { 40*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 41*4882a593Smuzhiyun device_type = "cpu"; 42*4882a593Smuzhiyun reg = <0x0 0x0>; 43*4882a593Smuzhiyun enable-method = "psci"; 44*4882a593Smuzhiyun next-level-cache = <&L2_0>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun cpu1: cpu@1 { 47*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 48*4882a593Smuzhiyun device_type = "cpu"; 49*4882a593Smuzhiyun reg = <0x0 0x1>; 50*4882a593Smuzhiyun enable-method = "psci"; 51*4882a593Smuzhiyun next-level-cache = <&L2_0>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun L2_0: l2-cache0 { 54*4882a593Smuzhiyun compatible = "cache"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun arm-pmu { 59*4882a593Smuzhiyun compatible = "arm,cortex-a53-pmu"; 60*4882a593Smuzhiyun interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 61*4882a593Smuzhiyun interrupt-affinity = <&cpu0>, <&cpu1>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun psci { 65*4882a593Smuzhiyun compatible = "arm,psci-0.2"; 66*4882a593Smuzhiyun method = "smc"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun timer { 70*4882a593Smuzhiyun compatible = "arm,armv8-timer"; 71*4882a593Smuzhiyun interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 72*4882a593Smuzhiyun <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 73*4882a593Smuzhiyun <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 74*4882a593Smuzhiyun <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun lcpll_clk: lcpll-clk { 78*4882a593Smuzhiyun compatible = "fixed-clock"; 79*4882a593Smuzhiyun #clock-cells = <0>; 80*4882a593Smuzhiyun clock-frequency = <2500000000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun clks: clock-controller@61110000c { 84*4882a593Smuzhiyun compatible = "microchip,sparx5-dpll"; 85*4882a593Smuzhiyun #clock-cells = <1>; 86*4882a593Smuzhiyun clocks = <&lcpll_clk>; 87*4882a593Smuzhiyun reg = <0x6 0x1110000c 0x24>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun ahb_clk: ahb-clk { 91*4882a593Smuzhiyun compatible = "fixed-clock"; 92*4882a593Smuzhiyun #clock-cells = <0>; 93*4882a593Smuzhiyun clock-frequency = <250000000>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun sys_clk: sys-clk { 97*4882a593Smuzhiyun compatible = "fixed-clock"; 98*4882a593Smuzhiyun #clock-cells = <0>; 99*4882a593Smuzhiyun clock-frequency = <625000000>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun axi: axi@600000000 { 103*4882a593Smuzhiyun compatible = "simple-bus"; 104*4882a593Smuzhiyun #address-cells = <2>; 105*4882a593Smuzhiyun #size-cells = <1>; 106*4882a593Smuzhiyun ranges; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun gic: interrupt-controller@600300000 { 109*4882a593Smuzhiyun compatible = "arm,gic-v3"; 110*4882a593Smuzhiyun #interrupt-cells = <3>; 111*4882a593Smuzhiyun #address-cells = <2>; 112*4882a593Smuzhiyun #size-cells = <2>; 113*4882a593Smuzhiyun interrupt-controller; 114*4882a593Smuzhiyun reg = <0x6 0x00300000 0x10000>, /* GIC Dist */ 115*4882a593Smuzhiyun <0x6 0x00340000 0xc0000>, /* GICR */ 116*4882a593Smuzhiyun <0x6 0x00200000 0x2000>, /* GICC */ 117*4882a593Smuzhiyun <0x6 0x00210000 0x2000>, /* GICV */ 118*4882a593Smuzhiyun <0x6 0x00220000 0x2000>; /* GICH */ 119*4882a593Smuzhiyun interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun cpu_ctrl: syscon@600000000 { 123*4882a593Smuzhiyun compatible = "microchip,sparx5-cpu-syscon", "syscon", 124*4882a593Smuzhiyun "simple-mfd"; 125*4882a593Smuzhiyun reg = <0x6 0x00000000 0xd0>; 126*4882a593Smuzhiyun mux: mux-controller { 127*4882a593Smuzhiyun compatible = "mmio-mux"; 128*4882a593Smuzhiyun #mux-control-cells = <0>; 129*4882a593Smuzhiyun /* 130*4882a593Smuzhiyun * SI_OWNER and SI2_OWNER in GENERAL_CTRL 131*4882a593Smuzhiyun * SPI: value 9 - (SIMC,SIBM) = 0b1001 132*4882a593Smuzhiyun * SPI2: value 6 - (SIBM,SIMC) = 0b0110 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun mux-reg-masks = <0x88 0xf0>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun uart0: serial@600100000 { 139*4882a593Smuzhiyun pinctrl-0 = <&uart_pins>; 140*4882a593Smuzhiyun pinctrl-names = "default"; 141*4882a593Smuzhiyun compatible = "ns16550a"; 142*4882a593Smuzhiyun reg = <0x6 0x00100000 0x20>; 143*4882a593Smuzhiyun clocks = <&ahb_clk>; 144*4882a593Smuzhiyun reg-io-width = <4>; 145*4882a593Smuzhiyun reg-shift = <2>; 146*4882a593Smuzhiyun interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun status = "disabled"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun uart1: serial@600102000 { 152*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins>; 153*4882a593Smuzhiyun pinctrl-names = "default"; 154*4882a593Smuzhiyun compatible = "ns16550a"; 155*4882a593Smuzhiyun reg = <0x6 0x00102000 0x20>; 156*4882a593Smuzhiyun clocks = <&ahb_clk>; 157*4882a593Smuzhiyun reg-io-width = <4>; 158*4882a593Smuzhiyun reg-shift = <2>; 159*4882a593Smuzhiyun interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun status = "disabled"; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun spi0: spi@600104000 { 165*4882a593Smuzhiyun #address-cells = <1>; 166*4882a593Smuzhiyun #size-cells = <0>; 167*4882a593Smuzhiyun compatible = "microchip,sparx5-spi"; 168*4882a593Smuzhiyun reg = <0x6 0x00104000 0x40>; 169*4882a593Smuzhiyun num-cs = <16>; 170*4882a593Smuzhiyun reg-io-width = <4>; 171*4882a593Smuzhiyun reg-shift = <2>; 172*4882a593Smuzhiyun clocks = <&ahb_clk>; 173*4882a593Smuzhiyun interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 174*4882a593Smuzhiyun status = "disabled"; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun timer1: timer@600105000 { 178*4882a593Smuzhiyun compatible = "snps,dw-apb-timer"; 179*4882a593Smuzhiyun reg = <0x6 0x00105000 0x1000>; 180*4882a593Smuzhiyun clocks = <&ahb_clk>; 181*4882a593Smuzhiyun clock-names = "timer"; 182*4882a593Smuzhiyun interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun sdhci0: mmc@600800000 { 186*4882a593Smuzhiyun compatible = "microchip,dw-sparx5-sdhci"; 187*4882a593Smuzhiyun status = "disabled"; 188*4882a593Smuzhiyun reg = <0x6 0x00800000 0x1000>; 189*4882a593Smuzhiyun pinctrl-0 = <&emmc_pins>; 190*4882a593Smuzhiyun pinctrl-names = "default"; 191*4882a593Smuzhiyun clocks = <&clks CLK_ID_AUX1>; 192*4882a593Smuzhiyun clock-names = "core"; 193*4882a593Smuzhiyun assigned-clocks = <&clks CLK_ID_AUX1>; 194*4882a593Smuzhiyun assigned-clock-rates = <800000000>; 195*4882a593Smuzhiyun interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 196*4882a593Smuzhiyun bus-width = <8>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun gpio: pinctrl@6110101e0 { 200*4882a593Smuzhiyun compatible = "microchip,sparx5-pinctrl"; 201*4882a593Smuzhiyun reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; 202*4882a593Smuzhiyun gpio-controller; 203*4882a593Smuzhiyun #gpio-cells = <2>; 204*4882a593Smuzhiyun gpio-ranges = <&gpio 0 0 64>; 205*4882a593Smuzhiyun interrupt-controller; 206*4882a593Smuzhiyun interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 207*4882a593Smuzhiyun #interrupt-cells = <2>; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun cs1_pins: cs1-pins { 210*4882a593Smuzhiyun pins = "GPIO_16"; 211*4882a593Smuzhiyun function = "si"; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun cs2_pins: cs2-pins { 215*4882a593Smuzhiyun pins = "GPIO_17"; 216*4882a593Smuzhiyun function = "si"; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun cs3_pins: cs3-pins { 220*4882a593Smuzhiyun pins = "GPIO_18"; 221*4882a593Smuzhiyun function = "si"; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun si2_pins: si2-pins { 225*4882a593Smuzhiyun pins = "GPIO_39", "GPIO_40", "GPIO_41"; 226*4882a593Smuzhiyun function = "si2"; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun uart_pins: uart-pins { 230*4882a593Smuzhiyun pins = "GPIO_10", "GPIO_11"; 231*4882a593Smuzhiyun function = "uart"; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun uart2_pins: uart2-pins { 235*4882a593Smuzhiyun pins = "GPIO_26", "GPIO_27"; 236*4882a593Smuzhiyun function = "uart2"; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun i2c_pins: i2c-pins { 240*4882a593Smuzhiyun pins = "GPIO_14", "GPIO_15"; 241*4882a593Smuzhiyun function = "twi"; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun i2c2_pins: i2c2-pins { 245*4882a593Smuzhiyun pins = "GPIO_28", "GPIO_29"; 246*4882a593Smuzhiyun function = "twi2"; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun emmc_pins: emmc-pins { 250*4882a593Smuzhiyun pins = "GPIO_34", "GPIO_35", "GPIO_36", 251*4882a593Smuzhiyun "GPIO_37", "GPIO_38", "GPIO_39", 252*4882a593Smuzhiyun "GPIO_40", "GPIO_41", "GPIO_42", 253*4882a593Smuzhiyun "GPIO_43", "GPIO_44", "GPIO_45", 254*4882a593Smuzhiyun "GPIO_46", "GPIO_47"; 255*4882a593Smuzhiyun function = "emmc"; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun i2c0: i2c@600101000 { 260*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 261*4882a593Smuzhiyun status = "disabled"; 262*4882a593Smuzhiyun pinctrl-0 = <&i2c_pins>; 263*4882a593Smuzhiyun pinctrl-names = "default"; 264*4882a593Smuzhiyun reg = <0x6 0x00101000 0x100>; 265*4882a593Smuzhiyun #address-cells = <1>; 266*4882a593Smuzhiyun #size-cells = <0>; 267*4882a593Smuzhiyun interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 268*4882a593Smuzhiyun i2c-sda-hold-time-ns = <300>; 269*4882a593Smuzhiyun clock-frequency = <100000>; 270*4882a593Smuzhiyun clocks = <&ahb_clk>; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun i2c1: i2c@600103000 { 274*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 275*4882a593Smuzhiyun status = "disabled"; 276*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 277*4882a593Smuzhiyun pinctrl-names = "default"; 278*4882a593Smuzhiyun reg = <0x6 0x00103000 0x100>; 279*4882a593Smuzhiyun #address-cells = <1>; 280*4882a593Smuzhiyun #size-cells = <0>; 281*4882a593Smuzhiyun interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 282*4882a593Smuzhiyun i2c-sda-hold-time-ns = <300>; 283*4882a593Smuzhiyun clock-frequency = <100000>; 284*4882a593Smuzhiyun clocks = <&ahb_clk>; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun tmon0: tmon@610508110 { 288*4882a593Smuzhiyun compatible = "microchip,sparx5-temp"; 289*4882a593Smuzhiyun reg = <0x6 0x10508110 0xc>; 290*4882a593Smuzhiyun #thermal-sensor-cells = <0>; 291*4882a593Smuzhiyun clocks = <&ahb_clk>; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun}; 295