1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2017 Marvell Technology Group Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree file for the Armada 80x0 SoC family 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun aliases { 10*4882a593Smuzhiyun gpio1 = &cp1_gpio1; 11*4882a593Smuzhiyun gpio2 = &cp0_gpio2; 12*4882a593Smuzhiyun spi1 = &cp0_spi0; 13*4882a593Smuzhiyun spi2 = &cp0_spi1; 14*4882a593Smuzhiyun spi3 = &cp1_spi0; 15*4882a593Smuzhiyun spi4 = &cp1_spi1; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/* 20*4882a593Smuzhiyun * Instantiate the master CP110 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun#define CP11X_NAME cp0 23*4882a593Smuzhiyun#define CP11X_BASE f2000000 24*4882a593Smuzhiyun#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000)) 25*4882a593Smuzhiyun#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 26*4882a593Smuzhiyun#define CP11X_PCIE0_BASE f2600000 27*4882a593Smuzhiyun#define CP11X_PCIE1_BASE f2620000 28*4882a593Smuzhiyun#define CP11X_PCIE2_BASE f2640000 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun#include "armada-cp110.dtsi" 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun#undef CP11X_NAME 33*4882a593Smuzhiyun#undef CP11X_BASE 34*4882a593Smuzhiyun#undef CP11X_PCIEx_MEM_BASE 35*4882a593Smuzhiyun#undef CP11X_PCIEx_MEM_SIZE 36*4882a593Smuzhiyun#undef CP11X_PCIE0_BASE 37*4882a593Smuzhiyun#undef CP11X_PCIE1_BASE 38*4882a593Smuzhiyun#undef CP11X_PCIE2_BASE 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun/* 41*4882a593Smuzhiyun * Instantiate the slave CP110 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun#define CP11X_NAME cp1 44*4882a593Smuzhiyun#define CP11X_BASE f4000000 45*4882a593Smuzhiyun#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000)) 46*4882a593Smuzhiyun#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000 47*4882a593Smuzhiyun#define CP11X_PCIE0_BASE f4600000 48*4882a593Smuzhiyun#define CP11X_PCIE1_BASE f4620000 49*4882a593Smuzhiyun#define CP11X_PCIE2_BASE f4640000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun#include "armada-cp110.dtsi" 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun#undef CP11X_NAME 54*4882a593Smuzhiyun#undef CP11X_BASE 55*4882a593Smuzhiyun#undef CP11X_PCIEx_MEM_BASE 56*4882a593Smuzhiyun#undef CP11X_PCIEx_MEM_SIZE 57*4882a593Smuzhiyun#undef CP11X_PCIE0_BASE 58*4882a593Smuzhiyun#undef CP11X_PCIE1_BASE 59*4882a593Smuzhiyun#undef CP11X_PCIE2_BASE 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun/* The 80x0 has two CP blocks, but uses only one block from each. */ 62*4882a593Smuzhiyun&cp1_gpio1 { 63*4882a593Smuzhiyun status = "okay"; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun&cp0_gpio2 { 67*4882a593Smuzhiyun status = "okay"; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&cp0_syscon0 { 71*4882a593Smuzhiyun cp0_pinctrl: pinctrl { 72*4882a593Smuzhiyun compatible = "marvell,armada-8k-cpm-pinctrl"; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun&cp1_syscon0 { 77*4882a593Smuzhiyun cp1_pinctrl: pinctrl { 78*4882a593Smuzhiyun compatible = "marvell,armada-8k-cps-pinctrl"; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun nand_pins: nand-pins { 81*4882a593Smuzhiyun marvell,pins = 82*4882a593Smuzhiyun "mpp0", "mpp1", "mpp2", "mpp3", 83*4882a593Smuzhiyun "mpp4", "mpp5", "mpp6", "mpp7", 84*4882a593Smuzhiyun "mpp8", "mpp9", "mpp10", "mpp11", 85*4882a593Smuzhiyun "mpp15", "mpp16", "mpp17", "mpp18", 86*4882a593Smuzhiyun "mpp19", "mpp20", "mpp21", "mpp22", 87*4882a593Smuzhiyun "mpp23", "mpp24", "mpp25", "mpp26", 88*4882a593Smuzhiyun "mpp27"; 89*4882a593Smuzhiyun marvell,function = "dev"; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun nand_rb: nand-rb { 93*4882a593Smuzhiyun marvell,pins = "mpp13", "mpp12"; 94*4882a593Smuzhiyun marvell,function = "nf"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&cp1_crypto { 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * The cryptographic engine found on the cp110 102*4882a593Smuzhiyun * master is enabled by default at the SoC 103*4882a593Smuzhiyun * level. Because it is not possible as of now 104*4882a593Smuzhiyun * to enable two cryptographic engines in 105*4882a593Smuzhiyun * parallel, disable this one by default. 106*4882a593Smuzhiyun */ 107*4882a593Smuzhiyun status = "disabled"; 108*4882a593Smuzhiyun}; 109