1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2016 Marvell Technology Group Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device Tree file for the Armada 8040 SoC, made of an AP806 Quad and 6*4882a593Smuzhiyun * two CP110. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "armada-ap806-quad.dtsi" 10*4882a593Smuzhiyun#include "armada-80x0.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Marvell Armada 8040"; 14*4882a593Smuzhiyun compatible = "marvell,armada8040", "marvell,armada-ap806-quad", 15*4882a593Smuzhiyun "marvell,armada-ap806"; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&cp0_pcie0 { 19*4882a593Smuzhiyun iommu-map = 20*4882a593Smuzhiyun <0x0 &smmu 0x480 0x20>, 21*4882a593Smuzhiyun <0x100 &smmu 0x4a0 0x20>, 22*4882a593Smuzhiyun <0x200 &smmu 0x4c0 0x20>; 23*4882a593Smuzhiyun iommu-map-mask = <0x031f>; 24*4882a593Smuzhiyun}; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock 27*4882a593Smuzhiyun * in CP master is not connected (by package) to the oscillator. So 28*4882a593Smuzhiyun * disable it. However, the RTC clock in CP slave is connected to the 29*4882a593Smuzhiyun * oscillator so this one is let enabled. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun&cp0_rtc { 32*4882a593Smuzhiyun status = "disabled"; 33*4882a593Smuzhiyun}; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun&cp0_sata0 { 36*4882a593Smuzhiyun iommus = <&smmu 0x444>; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&cp0_sdhci0 { 40*4882a593Smuzhiyun iommus = <&smmu 0x445>; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&cp0_usb3_0 { 44*4882a593Smuzhiyun iommus = <&smmu 0x440>; 45*4882a593Smuzhiyun}; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun&cp0_usb3_1 { 48*4882a593Smuzhiyun iommus = <&smmu 0x441>; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&cp1_sata0 { 52*4882a593Smuzhiyun iommus = <&smmu 0x454>; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&cp1_usb3_0 { 56*4882a593Smuzhiyun iommus = <&smmu 0x450>; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun&cp1_usb3_1 { 60*4882a593Smuzhiyun iommus = <&smmu 0x451>; 61*4882a593Smuzhiyun}; 62