1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Globalscale Marvell ESPRESSOBin Board 4*4882a593Smuzhiyun * Copyright (C) 2016 Marvell 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Romain Perier <romain.perier@free-electrons.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 11*4882a593Smuzhiyun#include "armada-372x.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun aliases { 15*4882a593Smuzhiyun ethernet0 = ð0; 16*4882a593Smuzhiyun /* for dsa slave device */ 17*4882a593Smuzhiyun ethernet1 = &switch0port1; 18*4882a593Smuzhiyun ethernet2 = &switch0port2; 19*4882a593Smuzhiyun ethernet3 = &switch0port3; 20*4882a593Smuzhiyun serial0 = &uart0; 21*4882a593Smuzhiyun serial1 = &uart1; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun chosen { 25*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun memory@0 { 29*4882a593Smuzhiyun device_type = "memory"; 30*4882a593Smuzhiyun reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun vcc_sd_reg1: regulator { 34*4882a593Smuzhiyun compatible = "regulator-gpio"; 35*4882a593Smuzhiyun regulator-name = "vcc_sd1"; 36*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 37*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 38*4882a593Smuzhiyun regulator-boot-on; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; 41*4882a593Smuzhiyun gpios-states = <0>; 42*4882a593Smuzhiyun states = <1800000 0x1 43*4882a593Smuzhiyun 3300000 0x0>; 44*4882a593Smuzhiyun enable-active-high; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun/* J9 */ 49*4882a593Smuzhiyun&pcie0 { 50*4882a593Smuzhiyun status = "okay"; 51*4882a593Smuzhiyun pinctrl-names = "default"; 52*4882a593Smuzhiyun pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 53*4882a593Smuzhiyun reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun/* J6 */ 57*4882a593Smuzhiyun&sata { 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun phys = <&comphy2 0>; 60*4882a593Smuzhiyun phy-names = "sata-phy"; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun/* J1 */ 64*4882a593Smuzhiyun&sdhci1 { 65*4882a593Smuzhiyun wp-inverted; 66*4882a593Smuzhiyun bus-width = <4>; 67*4882a593Smuzhiyun cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; 68*4882a593Smuzhiyun marvell,pad-type = "sd"; 69*4882a593Smuzhiyun vqmmc-supply = <&vcc_sd_reg1>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&sdio_pins>; 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun&spi0 { 77*4882a593Smuzhiyun status = "okay"; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun flash@0 { 80*4882a593Smuzhiyun reg = <0>; 81*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 82*4882a593Smuzhiyun spi-max-frequency = <104000000>; 83*4882a593Smuzhiyun m25p,fast-read; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun/* Exported on the micro USB connector J5 through an FTDI */ 88*4882a593Smuzhiyun&uart0 { 89*4882a593Smuzhiyun pinctrl-names = "default"; 90*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun/* 95*4882a593Smuzhiyun * Connector J17 and J18 expose a number of different features. Some pins are 96*4882a593Smuzhiyun * multiplexed. This is the case for instance for the following features: 97*4882a593Smuzhiyun * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of 98*4882a593Smuzhiyun * how to enable it. Beware that the signals are 1.8V TTL. 99*4882a593Smuzhiyun * - I2C 100*4882a593Smuzhiyun * - SPI 101*4882a593Smuzhiyun * - MMC 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun/* J7 */ 105*4882a593Smuzhiyun&usb3 { 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun/* J8 */ 110*4882a593Smuzhiyun&usb2 { 111*4882a593Smuzhiyun status = "okay"; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&mdio { 115*4882a593Smuzhiyun switch0: switch0@1 { 116*4882a593Smuzhiyun compatible = "marvell,mv88e6085"; 117*4882a593Smuzhiyun #address-cells = <1>; 118*4882a593Smuzhiyun #size-cells = <0>; 119*4882a593Smuzhiyun reg = <1>; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun dsa,member = <0 0>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun ports { 124*4882a593Smuzhiyun #address-cells = <1>; 125*4882a593Smuzhiyun #size-cells = <0>; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun switch0port0: port@0 { 128*4882a593Smuzhiyun reg = <0>; 129*4882a593Smuzhiyun label = "cpu"; 130*4882a593Smuzhiyun ethernet = <ð0>; 131*4882a593Smuzhiyun phy-mode = "rgmii-id"; 132*4882a593Smuzhiyun fixed-link { 133*4882a593Smuzhiyun speed = <1000>; 134*4882a593Smuzhiyun full-duplex; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun switch0port1: port@1 { 139*4882a593Smuzhiyun reg = <1>; 140*4882a593Smuzhiyun label = "wan"; 141*4882a593Smuzhiyun phy-handle = <&switch0phy0>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun switch0port2: port@2 { 145*4882a593Smuzhiyun reg = <2>; 146*4882a593Smuzhiyun label = "lan0"; 147*4882a593Smuzhiyun phy-handle = <&switch0phy1>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun switch0port3: port@3 { 151*4882a593Smuzhiyun reg = <3>; 152*4882a593Smuzhiyun label = "lan1"; 153*4882a593Smuzhiyun phy-handle = <&switch0phy2>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun mdio { 159*4882a593Smuzhiyun #address-cells = <1>; 160*4882a593Smuzhiyun #size-cells = <0>; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun switch0phy0: switch0phy0@11 { 163*4882a593Smuzhiyun reg = <0x11>; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun switch0phy1: switch0phy1@12 { 166*4882a593Smuzhiyun reg = <0x12>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun switch0phy2: switch0phy2@13 { 169*4882a593Smuzhiyun reg = <0x13>; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyunð0 { 176*4882a593Smuzhiyun pinctrl-names = "default"; 177*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins>, <&smi_pins>; 178*4882a593Smuzhiyun phy-mode = "rgmii-id"; 179*4882a593Smuzhiyun status = "okay"; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun fixed-link { 182*4882a593Smuzhiyun speed = <1000>; 183*4882a593Smuzhiyun full-duplex; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun}; 186