1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Marvell Armada 3720 development board 4*4882a593Smuzhiyun * (DB-88F3720-DDR3) 5*4882a593Smuzhiyun * Copyright (C) 2016 Marvell 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This file is compatible with the version 1.4 and the version 2.0 of 10*4882a593Smuzhiyun * the board, however the CON numbers are different between the 2 11*4882a593Smuzhiyun * version 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/dts-v1/; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 17*4882a593Smuzhiyun#include "armada-372x.dtsi" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/ { 20*4882a593Smuzhiyun model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; 21*4882a593Smuzhiyun compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun chosen { 24*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun memory@0 { 28*4882a593Smuzhiyun device_type = "memory"; 29*4882a593Smuzhiyun reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun exp_usb3_vbus: usb3-vbus { 33*4882a593Smuzhiyun compatible = "regulator-fixed"; 34*4882a593Smuzhiyun regulator-name = "usb3-vbus"; 35*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 36*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 37*4882a593Smuzhiyun enable-active-high; 38*4882a593Smuzhiyun regulator-always-on; 39*4882a593Smuzhiyun gpio = <&gpio_exp 1 GPIO_ACTIVE_HIGH>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun usb3_phy: usb3-phy { 43*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 44*4882a593Smuzhiyun vcc-supply = <&exp_usb3_vbus>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vcc_sd_reg1: regulator { 48*4882a593Smuzhiyun compatible = "regulator-gpio"; 49*4882a593Smuzhiyun regulator-name = "vcc_sd1"; 50*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 51*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 52*4882a593Smuzhiyun regulator-boot-on; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun gpios = <&gpiosb 23 GPIO_ACTIVE_HIGH>; 55*4882a593Smuzhiyun gpios-states = <0>; 56*4882a593Smuzhiyun states = <1800000 0x1 57*4882a593Smuzhiyun 3300000 0x0>; 58*4882a593Smuzhiyun enable-active-high; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun vcc_sd_reg2: regulator-vmcc { 62*4882a593Smuzhiyun compatible = "regulator-fixed"; 63*4882a593Smuzhiyun regulator-name = "vcc_sd2"; 64*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 65*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 66*4882a593Smuzhiyun regulator-boot-on; 67*4882a593Smuzhiyun enable-active-high; 68*4882a593Smuzhiyun gpio = <&gpio_exp 4 GPIO_ACTIVE_HIGH>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun/* Gigabit module on CON19(V2.0)/CON21(V1.4) */ 73*4882a593Smuzhiyunð0 { 74*4882a593Smuzhiyun pinctrl-names = "default"; 75*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins>; 76*4882a593Smuzhiyun phy-mode = "rgmii-id"; 77*4882a593Smuzhiyun phy = <&phy0>; 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun/* Gigabit module on CON18(V2.0)/CON20(V1.4) */ 82*4882a593Smuzhiyunð1 { 83*4882a593Smuzhiyun phy-mode = "sgmii"; 84*4882a593Smuzhiyun phy = <&phy1>; 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&i2c0 { 89*4882a593Smuzhiyun pinctrl-names = "default"; 90*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun gpio_exp: pca9555@22 { 94*4882a593Smuzhiyun compatible = "nxp,pca9555"; 95*4882a593Smuzhiyun gpio-controller; 96*4882a593Smuzhiyun #gpio-cells = <2>; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun reg = <0x22>; 99*4882a593Smuzhiyun /* 100*4882a593Smuzhiyun * IO0_0: PWR_EN_USB2 IO1_0: PWR_EN_VTT 101*4882a593Smuzhiyun * IO0_1: PWR_EN_USB23 IO1_1: MPCIE_WDISABLE 102*4882a593Smuzhiyun * IO0_2: PWR_EN_SATA IO1_2: RGMII_DEV_RSTN 103*4882a593Smuzhiyun * IO0_3: PWR_EN_PCIE IO1_3: SGMII_DEV_RSTN 104*4882a593Smuzhiyun * IO0_4: PWR_EN_SD 105*4882a593Smuzhiyun * IO0_5: PWR_EN_EMMC 106*4882a593Smuzhiyun * IO0_6: PWR_EN_RGMII IO1_6: SATA_USB3.0_SEL 107*4882a593Smuzhiyun * IO0_7: PWR_EN_SGMII IO1_7: PWR_MCI_PS 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun rtc@68 { 112*4882a593Smuzhiyun /* PT7C4337A from pericom fully compatible with the ds1337 */ 113*4882a593Smuzhiyun compatible = "dallas,ds1337"; 114*4882a593Smuzhiyun reg = <0x68>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun&mdio { 119*4882a593Smuzhiyun status = "okay"; 120*4882a593Smuzhiyun phy0: ethernet-phy@0 { 121*4882a593Smuzhiyun reg = <0>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun phy1: ethernet-phy@1 { 125*4882a593Smuzhiyun reg = <1>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ 130*4882a593Smuzhiyun&pcie0 { 131*4882a593Smuzhiyun pinctrl-names = "default"; 132*4882a593Smuzhiyun pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; 133*4882a593Smuzhiyun reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; 134*4882a593Smuzhiyun status = "okay"; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun/* CON3 */ 138*4882a593Smuzhiyun&sata { 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&sdhci0 { 143*4882a593Smuzhiyun non-removable; 144*4882a593Smuzhiyun bus-width = <8>; 145*4882a593Smuzhiyun mmc-ddr-1_8v; 146*4882a593Smuzhiyun mmc-hs400-1_8v; 147*4882a593Smuzhiyun marvell,pad-type = "fixed-1-8v"; 148*4882a593Smuzhiyun status = "okay"; 149*4882a593Smuzhiyun}; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun/* SD slot module on CON14(V2.0)/CON15(V1.4) */ 152*4882a593Smuzhiyun&sdhci1 { 153*4882a593Smuzhiyun wp-inverted; 154*4882a593Smuzhiyun cd-gpios = <&gpiosb 2 GPIO_ACTIVE_LOW>; 155*4882a593Smuzhiyun bus-width = <4>; 156*4882a593Smuzhiyun marvell,pad-type = "sd"; 157*4882a593Smuzhiyun vqmmc-supply = <&vcc_sd_reg1>; 158*4882a593Smuzhiyun vmmc-supply = <&vcc_sd_reg2>; 159*4882a593Smuzhiyun status = "okay"; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun&spi0 { 163*4882a593Smuzhiyun status = "okay"; 164*4882a593Smuzhiyun pinctrl-names = "default"; 165*4882a593Smuzhiyun pinctrl-0 = <&spi_quad_pins>; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun m25p80@0 { 168*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 169*4882a593Smuzhiyun reg = <0>; 170*4882a593Smuzhiyun spi-max-frequency = <108000000>; 171*4882a593Smuzhiyun spi-rx-bus-width = <4>; 172*4882a593Smuzhiyun spi-tx-bus-width = <4>; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun partitions { 175*4882a593Smuzhiyun compatible = "fixed-partitions"; 176*4882a593Smuzhiyun #address-cells = <1>; 177*4882a593Smuzhiyun #size-cells = <1>; 178*4882a593Smuzhiyun partition@0 { 179*4882a593Smuzhiyun label = "bootloader"; 180*4882a593Smuzhiyun reg = <0x0 0x200000>; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun partition@200000 { 183*4882a593Smuzhiyun label = "U-boot Env"; 184*4882a593Smuzhiyun reg = <0x200000 0x10000>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun partition@210000 { 187*4882a593Smuzhiyun label = "Linux"; 188*4882a593Smuzhiyun reg = <0x210000 0xDF0000>; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun/* 195*4882a593Smuzhiyun * Exported on the micro USB connector CON30(V2.0)/CON32(V1.4) through 196*4882a593Smuzhiyun * an FTDI (also on CON24(V2.0)/CON26(V1.4)). 197*4882a593Smuzhiyun */ 198*4882a593Smuzhiyun&uart0 { 199*4882a593Smuzhiyun pinctrl-names = "default"; 200*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 201*4882a593Smuzhiyun status = "okay"; 202*4882a593Smuzhiyun}; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun/* CON26(V2.0)/CON28(V1.4) */ 205*4882a593Smuzhiyun&uart1 { 206*4882a593Smuzhiyun pinctrl-names = "default"; 207*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins>; 208*4882a593Smuzhiyun status = "okay"; 209*4882a593Smuzhiyun}; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun/* CON27(V2.0)/CON29(V1.4) */ 212*4882a593Smuzhiyun&usb2 { 213*4882a593Smuzhiyun status = "okay"; 214*4882a593Smuzhiyun}; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun/* CON29(V2.0)/CON31(V1.4) */ 217*4882a593Smuzhiyun&usb3 { 218*4882a593Smuzhiyun status = "okay"; 219*4882a593Smuzhiyun usb-phy = <&usb3_phy>; 220*4882a593Smuzhiyun}; 221