1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2020, Intel Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Device tree describing Keem Bay SoC. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun interrupt-parent = <&gic>; 12*4882a593Smuzhiyun #address-cells = <2>; 13*4882a593Smuzhiyun #size-cells = <2>; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun cpus { 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <0>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun cpu@0 { 20*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 21*4882a593Smuzhiyun device_type = "cpu"; 22*4882a593Smuzhiyun reg = <0x0>; 23*4882a593Smuzhiyun enable-method = "psci"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun cpu@1 { 27*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 28*4882a593Smuzhiyun device_type = "cpu"; 29*4882a593Smuzhiyun reg = <0x1>; 30*4882a593Smuzhiyun enable-method = "psci"; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun cpu@2 { 34*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 35*4882a593Smuzhiyun device_type = "cpu"; 36*4882a593Smuzhiyun reg = <0x2>; 37*4882a593Smuzhiyun enable-method = "psci"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun cpu@3 { 41*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 42*4882a593Smuzhiyun device_type = "cpu"; 43*4882a593Smuzhiyun reg = <0x3>; 44*4882a593Smuzhiyun enable-method = "psci"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun psci { 49*4882a593Smuzhiyun compatible = "arm,psci-0.2"; 50*4882a593Smuzhiyun method = "smc"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun gic: interrupt-controller@20500000 { 54*4882a593Smuzhiyun compatible = "arm,gic-v3"; 55*4882a593Smuzhiyun interrupt-controller; 56*4882a593Smuzhiyun #interrupt-cells = <3>; 57*4882a593Smuzhiyun reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ 58*4882a593Smuzhiyun <0x0 0x20580000 0x0 0x80000>; /* GICR */ 59*4882a593Smuzhiyun /* VGIC maintenance interrupt */ 60*4882a593Smuzhiyun interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun timer { 64*4882a593Smuzhiyun compatible = "arm,armv8-timer"; 65*4882a593Smuzhiyun /* Secure, non-secure, virtual, and hypervisor */ 66*4882a593Smuzhiyun interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 67*4882a593Smuzhiyun <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 68*4882a593Smuzhiyun <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 69*4882a593Smuzhiyun <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun pmu { 73*4882a593Smuzhiyun compatible = "arm,armv8-pmuv3"; 74*4882a593Smuzhiyun interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun soc { 78*4882a593Smuzhiyun compatible = "simple-bus"; 79*4882a593Smuzhiyun #address-cells = <2>; 80*4882a593Smuzhiyun #size-cells = <2>; 81*4882a593Smuzhiyun ranges; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun uart0: serial@20150000 { 84*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 85*4882a593Smuzhiyun reg = <0x0 0x20150000 0x0 0x100>; 86*4882a593Smuzhiyun interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 87*4882a593Smuzhiyun clock-frequency = <24000000>; 88*4882a593Smuzhiyun reg-shift = <2>; 89*4882a593Smuzhiyun reg-io-width = <4>; 90*4882a593Smuzhiyun status = "disabled"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun uart1: serial@20160000 { 94*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 95*4882a593Smuzhiyun reg = <0x0 0x20160000 0x0 0x100>; 96*4882a593Smuzhiyun interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 97*4882a593Smuzhiyun clock-frequency = <24000000>; 98*4882a593Smuzhiyun reg-shift = <2>; 99*4882a593Smuzhiyun reg-io-width = <4>; 100*4882a593Smuzhiyun status = "disabled"; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun uart2: serial@20170000 { 104*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 105*4882a593Smuzhiyun reg = <0x0 0x20170000 0x0 0x100>; 106*4882a593Smuzhiyun interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 107*4882a593Smuzhiyun clock-frequency = <24000000>; 108*4882a593Smuzhiyun reg-shift = <2>; 109*4882a593Smuzhiyun reg-io-width = <4>; 110*4882a593Smuzhiyun status = "disabled"; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun uart3: serial@20180000 { 114*4882a593Smuzhiyun compatible = "snps,dw-apb-uart"; 115*4882a593Smuzhiyun reg = <0x0 0x20180000 0x0 0x100>; 116*4882a593Smuzhiyun interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 117*4882a593Smuzhiyun clock-frequency = <24000000>; 118*4882a593Smuzhiyun reg-shift = <2>; 119*4882a593Smuzhiyun reg-io-width = <4>; 120*4882a593Smuzhiyun status = "disabled"; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun}; 124