1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2017~2018 NXP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "imx8qxp.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Freescale i.MX8QXP MEK"; 12*4882a593Smuzhiyun compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun chosen { 15*4882a593Smuzhiyun stdout-path = &adma_lpuart0; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun memory@80000000 { 19*4882a593Smuzhiyun device_type = "memory"; 20*4882a593Smuzhiyun reg = <0x00000000 0x80000000 0 0x40000000>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg_usdhc2_vmmc: usdhc2-vmmc { 24*4882a593Smuzhiyun compatible = "regulator-fixed"; 25*4882a593Smuzhiyun regulator-name = "SD1_SPWR"; 26*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 27*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 28*4882a593Smuzhiyun gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; 29*4882a593Smuzhiyun enable-active-high; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun&adma_dsp { 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&adma_i2c1 { 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <0>; 40*4882a593Smuzhiyun clock-frequency = <100000>; 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun i2c-switch@71 { 46*4882a593Smuzhiyun compatible = "nxp,pca9646", "nxp,pca9546"; 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <0>; 49*4882a593Smuzhiyun reg = <0x71>; 50*4882a593Smuzhiyun reset-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_LOW>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun i2c@0 { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <0>; 55*4882a593Smuzhiyun reg = <0>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun max7322: gpio@68 { 58*4882a593Smuzhiyun compatible = "maxim,max7322"; 59*4882a593Smuzhiyun reg = <0x68>; 60*4882a593Smuzhiyun gpio-controller; 61*4882a593Smuzhiyun #gpio-cells = <2>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun i2c@1 { 66*4882a593Smuzhiyun #address-cells = <1>; 67*4882a593Smuzhiyun #size-cells = <0>; 68*4882a593Smuzhiyun reg = <1>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun i2c@2 { 72*4882a593Smuzhiyun #address-cells = <1>; 73*4882a593Smuzhiyun #size-cells = <0>; 74*4882a593Smuzhiyun reg = <2>; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun pressure-sensor@60 { 77*4882a593Smuzhiyun compatible = "fsl,mpl3115"; 78*4882a593Smuzhiyun reg = <0x60>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun i2c@3 { 83*4882a593Smuzhiyun #address-cells = <1>; 84*4882a593Smuzhiyun #size-cells = <0>; 85*4882a593Smuzhiyun reg = <3>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun pca9557_a: gpio@1a { 88*4882a593Smuzhiyun compatible = "nxp,pca9557"; 89*4882a593Smuzhiyun reg = <0x1a>; 90*4882a593Smuzhiyun gpio-controller; 91*4882a593Smuzhiyun #gpio-cells = <2>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun pca9557_b: gpio@1d { 95*4882a593Smuzhiyun compatible = "nxp,pca9557"; 96*4882a593Smuzhiyun reg = <0x1d>; 97*4882a593Smuzhiyun gpio-controller; 98*4882a593Smuzhiyun #gpio-cells = <2>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun light-sensor@44 { 102*4882a593Smuzhiyun pinctrl-names = "default"; 103*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_isl29023>; 104*4882a593Smuzhiyun compatible = "isil,isl29023"; 105*4882a593Smuzhiyun reg = <0x44>; 106*4882a593Smuzhiyun interrupt-parent = <&lsio_gpio1>; 107*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&adma_lpuart0 { 114*4882a593Smuzhiyun pinctrl-names = "default"; 115*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_lpuart0>; 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun&fec1 { 120*4882a593Smuzhiyun pinctrl-names = "default"; 121*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fec1>; 122*4882a593Smuzhiyun phy-mode = "rgmii-id"; 123*4882a593Smuzhiyun phy-handle = <ðphy0>; 124*4882a593Smuzhiyun fsl,magic-packet; 125*4882a593Smuzhiyun status = "okay"; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun mdio { 128*4882a593Smuzhiyun #address-cells = <1>; 129*4882a593Smuzhiyun #size-cells = <0>; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 132*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 133*4882a593Smuzhiyun reg = <0>; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&scu_key { 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&thermal_zones { 143*4882a593Smuzhiyun pmic-thermal0 { 144*4882a593Smuzhiyun polling-delay-passive = <250>; 145*4882a593Smuzhiyun polling-delay = <2000>; 146*4882a593Smuzhiyun thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun trips { 149*4882a593Smuzhiyun pmic_alert0: trip0 { 150*4882a593Smuzhiyun temperature = <110000>; 151*4882a593Smuzhiyun hysteresis = <2000>; 152*4882a593Smuzhiyun type = "passive"; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun pmic_crit0: trip1 { 156*4882a593Smuzhiyun temperature = <125000>; 157*4882a593Smuzhiyun hysteresis = <2000>; 158*4882a593Smuzhiyun type = "critical"; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun cooling-maps { 163*4882a593Smuzhiyun map0 { 164*4882a593Smuzhiyun trip = <&pmic_alert0>; 165*4882a593Smuzhiyun cooling-device = 166*4882a593Smuzhiyun <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 167*4882a593Smuzhiyun <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 168*4882a593Smuzhiyun <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 169*4882a593Smuzhiyun <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun }; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun&usdhc1 { 176*4882a593Smuzhiyun assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; 177*4882a593Smuzhiyun assigned-clock-rates = <200000000>; 178*4882a593Smuzhiyun pinctrl-names = "default"; 179*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc1>; 180*4882a593Smuzhiyun bus-width = <8>; 181*4882a593Smuzhiyun no-sd; 182*4882a593Smuzhiyun no-sdio; 183*4882a593Smuzhiyun non-removable; 184*4882a593Smuzhiyun status = "okay"; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&usdhc2 { 188*4882a593Smuzhiyun assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; 189*4882a593Smuzhiyun assigned-clock-rates = <200000000>; 190*4882a593Smuzhiyun pinctrl-names = "default"; 191*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usdhc2>; 192*4882a593Smuzhiyun bus-width = <4>; 193*4882a593Smuzhiyun vmmc-supply = <®_usdhc2_vmmc>; 194*4882a593Smuzhiyun cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; 195*4882a593Smuzhiyun wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; 196*4882a593Smuzhiyun status = "okay"; 197*4882a593Smuzhiyun}; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun&iomuxc { 200*4882a593Smuzhiyun pinctrl_fec1: fec1grp { 201*4882a593Smuzhiyun fsl,pins = < 202*4882a593Smuzhiyun IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 203*4882a593Smuzhiyun IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 204*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 205*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 206*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 207*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 208*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 209*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 210*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 211*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 212*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 213*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 214*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 215*4882a593Smuzhiyun IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 216*4882a593Smuzhiyun >; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun pinctrl_ioexp_rst: ioexprstgrp { 220*4882a593Smuzhiyun fsl,pins = < 221*4882a593Smuzhiyun IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 222*4882a593Smuzhiyun >; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun pinctrl_isl29023: isl29023grp { 226*4882a593Smuzhiyun fsl,pins = < 227*4882a593Smuzhiyun IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 228*4882a593Smuzhiyun >; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun pinctrl_lpi2c1: lpi2c1grp { 232*4882a593Smuzhiyun fsl,pins = < 233*4882a593Smuzhiyun IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 234*4882a593Smuzhiyun IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 235*4882a593Smuzhiyun >; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun pinctrl_lpuart0: lpuart0grp { 239*4882a593Smuzhiyun fsl,pins = < 240*4882a593Smuzhiyun IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 241*4882a593Smuzhiyun IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 242*4882a593Smuzhiyun >; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun pinctrl_usdhc1: usdhc1grp { 246*4882a593Smuzhiyun fsl,pins = < 247*4882a593Smuzhiyun IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 248*4882a593Smuzhiyun IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 249*4882a593Smuzhiyun IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 250*4882a593Smuzhiyun IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 251*4882a593Smuzhiyun IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 252*4882a593Smuzhiyun IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 253*4882a593Smuzhiyun IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 254*4882a593Smuzhiyun IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 255*4882a593Smuzhiyun IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 256*4882a593Smuzhiyun IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 257*4882a593Smuzhiyun IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 258*4882a593Smuzhiyun >; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun pinctrl_usdhc2: usdhc2grp { 262*4882a593Smuzhiyun fsl,pins = < 263*4882a593Smuzhiyun IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 264*4882a593Smuzhiyun IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 265*4882a593Smuzhiyun IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 266*4882a593Smuzhiyun IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 267*4882a593Smuzhiyun IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 268*4882a593Smuzhiyun IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 269*4882a593Smuzhiyun IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 270*4882a593Smuzhiyun >; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun}; 273