xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2018 Einfochips
4*4882a593Smuzhiyun * Copyright 2019 Linaro Ltd.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "imx8qxp.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "Einfochips i.MX8QXP AI_ML";
13*4882a593Smuzhiyun	compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	aliases {
16*4882a593Smuzhiyun		serial1 = &adma_lpuart1;
17*4882a593Smuzhiyun		serial2 = &adma_lpuart2;
18*4882a593Smuzhiyun		serial3 = &adma_lpuart3;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	chosen {
22*4882a593Smuzhiyun		stdout-path = &adma_lpuart2;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	memory@80000000 {
26*4882a593Smuzhiyun		device_type = "memory";
27*4882a593Smuzhiyun		reg = <0x00000000 0x80000000 0 0x80000000>;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	leds {
31*4882a593Smuzhiyun		compatible = "gpio-leds";
32*4882a593Smuzhiyun		pinctrl-names = "default";
33*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_leds>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		user-led1 {
36*4882a593Smuzhiyun			label = "green:user1";
37*4882a593Smuzhiyun			gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>;
38*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		user-led2 {
42*4882a593Smuzhiyun			label = "green:user2";
43*4882a593Smuzhiyun			gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>;
44*4882a593Smuzhiyun			linux,default-trigger = "none";
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun		user-led3 {
48*4882a593Smuzhiyun			label = "green:user3";
49*4882a593Smuzhiyun			gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>;
50*4882a593Smuzhiyun			linux,default-trigger = "mmc1";
51*4882a593Smuzhiyun			default-state = "off";
52*4882a593Smuzhiyun		};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		user-led4 {
55*4882a593Smuzhiyun			label = "green:user4";
56*4882a593Smuzhiyun			gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
57*4882a593Smuzhiyun			panic-indicator;
58*4882a593Smuzhiyun			linux,default-trigger = "none";
59*4882a593Smuzhiyun		};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun		wlan-active-led {
62*4882a593Smuzhiyun			label = "yellow:wlan";
63*4882a593Smuzhiyun			gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>;
64*4882a593Smuzhiyun			linux,default-trigger = "phy0tx";
65*4882a593Smuzhiyun			default-state = "off";
66*4882a593Smuzhiyun		};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun		bt-active-led {
69*4882a593Smuzhiyun			label = "blue:bt";
70*4882a593Smuzhiyun			gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>;
71*4882a593Smuzhiyun			linux,default-trigger = "hci0-power";
72*4882a593Smuzhiyun			default-state = "off";
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
77*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
78*4882a593Smuzhiyun		pinctrl-names = "default";
79*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_wifi_reg_on>;
80*4882a593Smuzhiyun		reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun/* BT */
85*4882a593Smuzhiyun&adma_lpuart0 {
86*4882a593Smuzhiyun	pinctrl-names = "default";
87*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lpuart0>;
88*4882a593Smuzhiyun	uart-has-rtscts;
89*4882a593Smuzhiyun	status = "okay";
90*4882a593Smuzhiyun};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun/* LS-UART0 */
93*4882a593Smuzhiyun&adma_lpuart1 {
94*4882a593Smuzhiyun	pinctrl-names = "default";
95*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lpuart1>;
96*4882a593Smuzhiyun	status = "okay";
97*4882a593Smuzhiyun};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun/* Debug */
100*4882a593Smuzhiyun&adma_lpuart2 {
101*4882a593Smuzhiyun	pinctrl-names = "default";
102*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lpuart2>;
103*4882a593Smuzhiyun	status = "okay";
104*4882a593Smuzhiyun};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun/* PCI-E UART */
107*4882a593Smuzhiyun&adma_lpuart3 {
108*4882a593Smuzhiyun	pinctrl-names = "default";
109*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_lpuart3>;
110*4882a593Smuzhiyun	status = "okay";
111*4882a593Smuzhiyun};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun&fec1 {
114*4882a593Smuzhiyun	pinctrl-names = "default";
115*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_fec1>;
116*4882a593Smuzhiyun	phy-mode = "rgmii-id";
117*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
118*4882a593Smuzhiyun	fsl,magic-packet;
119*4882a593Smuzhiyun	status = "okay";
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	mdio {
122*4882a593Smuzhiyun		#address-cells = <1>;
123*4882a593Smuzhiyun		#size-cells = <0>;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun		ethphy0: ethernet-phy@0 {
126*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c22";
127*4882a593Smuzhiyun			reg = <0>;
128*4882a593Smuzhiyun		};
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun/* WiFi */
133*4882a593Smuzhiyun&usdhc1 {
134*4882a593Smuzhiyun	#address-cells = <1>;
135*4882a593Smuzhiyun	#size-cells = <0>;
136*4882a593Smuzhiyun	assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
137*4882a593Smuzhiyun	assigned-clock-rates = <200000000>;
138*4882a593Smuzhiyun	pinctrl-names = "default";
139*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
140*4882a593Smuzhiyun	bus-width = <4>;
141*4882a593Smuzhiyun	no-sd;
142*4882a593Smuzhiyun	non-removable;
143*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
144*4882a593Smuzhiyun	status = "okay";
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun	brcmf: wifi@1 {
147*4882a593Smuzhiyun		reg = <1>;
148*4882a593Smuzhiyun		compatible = "brcm,bcm4329-fmac";
149*4882a593Smuzhiyun	};
150*4882a593Smuzhiyun};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun/* SD */
153*4882a593Smuzhiyun&usdhc2 {
154*4882a593Smuzhiyun	assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
155*4882a593Smuzhiyun	assigned-clock-rates = <200000000>;
156*4882a593Smuzhiyun	pinctrl-names = "default";
157*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
158*4882a593Smuzhiyun	bus-width = <4>;
159*4882a593Smuzhiyun	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
160*4882a593Smuzhiyun	status = "okay";
161*4882a593Smuzhiyun};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun&iomuxc {
164*4882a593Smuzhiyun	pinctrl_fec1: fec1grp {
165*4882a593Smuzhiyun		fsl,pins = <
166*4882a593Smuzhiyun			IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020
167*4882a593Smuzhiyun			IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
168*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
169*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
170*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
171*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
172*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
173*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
174*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
175*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
176*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
177*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
178*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
179*4882a593Smuzhiyun			IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
180*4882a593Smuzhiyun		>;
181*4882a593Smuzhiyun	};
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun	pinctrl_leds: ledsgrp{
184*4882a593Smuzhiyun		fsl,pins = <
185*4882a593Smuzhiyun			IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06			0x00000021
186*4882a593Smuzhiyun			IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07			0x00000021
187*4882a593Smuzhiyun			IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16			0x00000021
188*4882a593Smuzhiyun			IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21			0x00000021
189*4882a593Smuzhiyun			IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17			0x00000021
190*4882a593Smuzhiyun			IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18			0x00000021
191*4882a593Smuzhiyun		>;
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	pinctrl_lpuart0: lpuart0grp {
195*4882a593Smuzhiyun		fsl,pins = <
196*4882a593Smuzhiyun			IMX8QXP_UART0_RX_ADMA_UART0_RX				0X06000020
197*4882a593Smuzhiyun			IMX8QXP_UART0_TX_ADMA_UART0_TX				0X06000020
198*4882a593Smuzhiyun			IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 			0x06000020
199*4882a593Smuzhiyun			IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B			0x06000020
200*4882a593Smuzhiyun		>;
201*4882a593Smuzhiyun	};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun	pinctrl_lpuart1: lpuart1grp {
204*4882a593Smuzhiyun		fsl,pins = <
205*4882a593Smuzhiyun			IMX8QXP_UART1_RX_ADMA_UART1_RX				0X06000020
206*4882a593Smuzhiyun			IMX8QXP_UART1_TX_ADMA_UART1_TX				0X06000020
207*4882a593Smuzhiyun		>;
208*4882a593Smuzhiyun	};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun	pinctrl_lpuart2: lpuart2grp {
211*4882a593Smuzhiyun		fsl,pins = <
212*4882a593Smuzhiyun			IMX8QXP_UART2_RX_ADMA_UART2_RX				0X06000020
213*4882a593Smuzhiyun			IMX8QXP_UART2_TX_ADMA_UART2_TX				0X06000020
214*4882a593Smuzhiyun		>;
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	pinctrl_lpuart3: lpuart3grp {
218*4882a593Smuzhiyun		fsl,pins = <
219*4882a593Smuzhiyun			IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX			0X06000020
220*4882a593Smuzhiyun			IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX			0X06000020
221*4882a593Smuzhiyun		>;
222*4882a593Smuzhiyun	};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
225*4882a593Smuzhiyun		fsl,pins = <
226*4882a593Smuzhiyun			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
227*4882a593Smuzhiyun			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x00000021
228*4882a593Smuzhiyun			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
229*4882a593Smuzhiyun			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
230*4882a593Smuzhiyun			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
231*4882a593Smuzhiyun			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
232*4882a593Smuzhiyun		>;
233*4882a593Smuzhiyun	};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
236*4882a593Smuzhiyun		fsl,pins = <
237*4882a593Smuzhiyun			IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
238*4882a593Smuzhiyun			IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
239*4882a593Smuzhiyun			IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
240*4882a593Smuzhiyun			IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
241*4882a593Smuzhiyun			IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
242*4882a593Smuzhiyun			IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
243*4882a593Smuzhiyun			IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
244*4882a593Smuzhiyun			IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22			0x00000021
245*4882a593Smuzhiyun		>;
246*4882a593Smuzhiyun	};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun	pinctrl_wifi_reg_on: wifiregongrp {
249*4882a593Smuzhiyun		fsl,pins = <
250*4882a593Smuzhiyun			IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24			0x00000021
251*4882a593Smuzhiyun		>;
252*4882a593Smuzhiyun	};
253*4882a593Smuzhiyun};
254