xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2018-2019 Purism SPC
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "dt-bindings/input/input.h"
9*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
10*4882a593Smuzhiyun#include "dt-bindings/pwm/pwm.h"
11*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
12*4882a593Smuzhiyun#include "imx8mq.dtsi"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "Purism Librem 5 devkit";
16*4882a593Smuzhiyun	compatible = "purism,librem5-devkit", "fsl,imx8mq";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	backlight_dsi: backlight-dsi {
19*4882a593Smuzhiyun		compatible = "pwm-backlight";
20*4882a593Smuzhiyun		/* 200 Hz for the PAM2841 */
21*4882a593Smuzhiyun		pwms = <&pwm1 0 5000000>;
22*4882a593Smuzhiyun		brightness-levels = <0 100>;
23*4882a593Smuzhiyun		num-interpolated-steps = <100>;
24*4882a593Smuzhiyun		/* Default brightness level (index into the array defined by */
25*4882a593Smuzhiyun		/* the "brightness-levels" property) */
26*4882a593Smuzhiyun		default-brightness-level = <0>;
27*4882a593Smuzhiyun		power-supply = <&reg_22v4_p>;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	chosen {
31*4882a593Smuzhiyun		stdout-path = &uart1;
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	gpio-keys {
35*4882a593Smuzhiyun		compatible = "gpio-keys";
36*4882a593Smuzhiyun		pinctrl-names = "default";
37*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_keys>;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		btn1 {
40*4882a593Smuzhiyun			label = "VOL_UP";
41*4882a593Smuzhiyun			gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
42*4882a593Smuzhiyun			wakeup-source;
43*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		btn2 {
47*4882a593Smuzhiyun			label = "VOL_DOWN";
48*4882a593Smuzhiyun			gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
49*4882a593Smuzhiyun			wakeup-source;
50*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		hp-det {
54*4882a593Smuzhiyun			label = "HP_DET";
55*4882a593Smuzhiyun			gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
56*4882a593Smuzhiyun			wakeup-source;
57*4882a593Smuzhiyun			linux,code = <KEY_HP>;
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		wwan-wake {
61*4882a593Smuzhiyun			label = "WWAN_WAKE";
62*4882a593Smuzhiyun			gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
63*4882a593Smuzhiyun			interrupt-parent = <&gpio3>;
64*4882a593Smuzhiyun			interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
65*4882a593Smuzhiyun			wakeup-source;
66*4882a593Smuzhiyun			linux,code = <KEY_PHONE>;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	leds {
71*4882a593Smuzhiyun		compatible = "gpio-leds";
72*4882a593Smuzhiyun		pinctrl-names = "default";
73*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_leds>;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun		led1 {
76*4882a593Smuzhiyun			label = "LED 1";
77*4882a593Smuzhiyun			gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
78*4882a593Smuzhiyun			default-state = "off";
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	pmic_osc: clock-pmic {
83*4882a593Smuzhiyun		compatible = "fixed-clock";
84*4882a593Smuzhiyun		#clock-cells = <0>;
85*4882a593Smuzhiyun		clock-frequency = <32768>;
86*4882a593Smuzhiyun		clock-output-names = "pmic_osc";
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	reg_1v8_p: regulator-1v8-p {
90*4882a593Smuzhiyun		compatible = "regulator-fixed";
91*4882a593Smuzhiyun		regulator-name = "1v8_p";
92*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
93*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
94*4882a593Smuzhiyun		vin-supply = <&reg_pwr_en>;
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	reg_2v8_p: regulator-2v8-p {
98*4882a593Smuzhiyun		compatible = "regulator-fixed";
99*4882a593Smuzhiyun		regulator-name = "2v8_p";
100*4882a593Smuzhiyun		regulator-min-microvolt = <2800000>;
101*4882a593Smuzhiyun		regulator-max-microvolt = <2800000>;
102*4882a593Smuzhiyun		vin-supply = <&reg_pwr_en>;
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	reg_3v3_p: regulator-3v3-p {
106*4882a593Smuzhiyun		compatible = "regulator-fixed";
107*4882a593Smuzhiyun		regulator-name = "3v3_p";
108*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
109*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
110*4882a593Smuzhiyun		vin-supply = <&reg_pwr_en>;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun		regulator-state-mem {
113*4882a593Smuzhiyun			regulator-on-in-suspend;
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	reg_5v_p: regulator-5v-p {
118*4882a593Smuzhiyun		compatible = "regulator-fixed";
119*4882a593Smuzhiyun		regulator-name = "5v_p";
120*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
121*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
122*4882a593Smuzhiyun		vin-supply = <&reg_pwr_en>;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		regulator-state-mem {
125*4882a593Smuzhiyun			regulator-on-in-suspend;
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	reg_22v4_p: regulator-22v4-p  {
130*4882a593Smuzhiyun		compatible = "regulator-fixed";
131*4882a593Smuzhiyun		regulator-name = "22v4_P";
132*4882a593Smuzhiyun		regulator-min-microvolt = <22400000>;
133*4882a593Smuzhiyun		regulator-max-microvolt = <22400000>;
134*4882a593Smuzhiyun		vin-supply = <&reg_pwr_en>;
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	reg_pwr_en: regulator-pwr-en {
138*4882a593Smuzhiyun		compatible = "regulator-fixed";
139*4882a593Smuzhiyun		pinctrl-names = "default";
140*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pwr_en>;
141*4882a593Smuzhiyun		regulator-name = "PWR_EN";
142*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
143*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
144*4882a593Smuzhiyun		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
145*4882a593Smuzhiyun		enable-active-high;
146*4882a593Smuzhiyun		regulator-always-on;
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
150*4882a593Smuzhiyun		compatible = "regulator-fixed";
151*4882a593Smuzhiyun		pinctrl-names = "default";
152*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usdhc2_pwr>;
153*4882a593Smuzhiyun		regulator-name = "VSD_3V3";
154*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
155*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
156*4882a593Smuzhiyun		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
157*4882a593Smuzhiyun		enable-active-high;
158*4882a593Smuzhiyun		regulator-always-on;
159*4882a593Smuzhiyun	};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	wwan_codec: sound-wwan-codec {
162*4882a593Smuzhiyun		compatible = "option,gtm601";
163*4882a593Smuzhiyun		#sound-dai-cells = <0>;
164*4882a593Smuzhiyun	};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun	sound {
167*4882a593Smuzhiyun		compatible = "simple-audio-card";
168*4882a593Smuzhiyun		simple-audio-card,name = "sgtl5000";
169*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
170*4882a593Smuzhiyun		simple-audio-card,widgets =
171*4882a593Smuzhiyun			"Microphone", "Microphone Jack",
172*4882a593Smuzhiyun			"Headphone", "Headphone Jack",
173*4882a593Smuzhiyun			"Speaker", "Speaker Ext",
174*4882a593Smuzhiyun			"Line", "Line In Jack";
175*4882a593Smuzhiyun		simple-audio-card,routing =
176*4882a593Smuzhiyun			"MIC_IN", "Microphone Jack",
177*4882a593Smuzhiyun			"Microphone Jack", "Mic Bias",
178*4882a593Smuzhiyun			"LINE_IN", "Line In Jack",
179*4882a593Smuzhiyun			"Headphone Jack", "HP_OUT",
180*4882a593Smuzhiyun			"Speaker Ext", "LINE_OUT";
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		simple-audio-card,cpu {
183*4882a593Smuzhiyun			sound-dai = <&sai2>;
184*4882a593Smuzhiyun		};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun		simple-audio-card,codec {
187*4882a593Smuzhiyun			sound-dai = <&sgtl5000>;
188*4882a593Smuzhiyun			clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
189*4882a593Smuzhiyun			frame-master;
190*4882a593Smuzhiyun			bitclock-master;
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	sound-wwan {
195*4882a593Smuzhiyun		compatible = "simple-audio-card";
196*4882a593Smuzhiyun		simple-audio-card,name = "SIMCom SIM7100";
197*4882a593Smuzhiyun		simple-audio-card,format = "dsp_a";
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun		simple-audio-card,cpu {
200*4882a593Smuzhiyun			sound-dai = <&sai6>;
201*4882a593Smuzhiyun		};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun		telephony_link_master: simple-audio-card,codec {
204*4882a593Smuzhiyun			sound-dai = <&wwan_codec>;
205*4882a593Smuzhiyun			frame-master;
206*4882a593Smuzhiyun			bitclock-master;
207*4882a593Smuzhiyun		};
208*4882a593Smuzhiyun	};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun	vibrator {
211*4882a593Smuzhiyun		compatible = "gpio-vibrator";
212*4882a593Smuzhiyun		pinctrl-names = "default";
213*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_haptic>;
214*4882a593Smuzhiyun	        enable-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
215*4882a593Smuzhiyun		vcc-supply = <&reg_3v3_p>;
216*4882a593Smuzhiyun	};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun	wifi_pwr_en: regulator-wifi-en {
219*4882a593Smuzhiyun		compatible = "regulator-fixed";
220*4882a593Smuzhiyun		pinctrl-names = "default";
221*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_wifi_pwr_en>;
222*4882a593Smuzhiyun		regulator-name = "WIFI_EN";
223*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
224*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
225*4882a593Smuzhiyun		gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
226*4882a593Smuzhiyun		enable-active-high;
227*4882a593Smuzhiyun		regulator-always-on;
228*4882a593Smuzhiyun	};
229*4882a593Smuzhiyun};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun&A53_0 {
232*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
233*4882a593Smuzhiyun};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun&A53_1 {
236*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
237*4882a593Smuzhiyun};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun&A53_2 {
240*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
241*4882a593Smuzhiyun};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun&A53_3 {
244*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
245*4882a593Smuzhiyun};
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun&clk {
248*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
249*4882a593Smuzhiyun	assigned-clock-rates = <786432000>, <722534400>;
250*4882a593Smuzhiyun};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun&dphy {
253*4882a593Smuzhiyun	status = "okay";
254*4882a593Smuzhiyun};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun&fec1 {
257*4882a593Smuzhiyun	pinctrl-names = "default";
258*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_fec1>;
259*4882a593Smuzhiyun	phy-mode = "rgmii-id";
260*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
261*4882a593Smuzhiyun	fsl,magic-packet;
262*4882a593Smuzhiyun	phy-supply = <&reg_3v3_p>;
263*4882a593Smuzhiyun	status = "okay";
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	mdio {
266*4882a593Smuzhiyun		#address-cells = <1>;
267*4882a593Smuzhiyun		#size-cells = <0>;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun		ethphy0: ethernet-phy@1 {
270*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c22";
271*4882a593Smuzhiyun			reg = <1>;
272*4882a593Smuzhiyun		};
273*4882a593Smuzhiyun	};
274*4882a593Smuzhiyun};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun&i2c1 {
277*4882a593Smuzhiyun	clock-frequency = <100000>;
278*4882a593Smuzhiyun	pinctrl-names = "default";
279*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
280*4882a593Smuzhiyun	status = "okay";
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun	pmic: pmic@4b {
283*4882a593Smuzhiyun		compatible = "rohm,bd71837";
284*4882a593Smuzhiyun		reg = <0x4b>;
285*4882a593Smuzhiyun		pinctrl-names = "default";
286*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pmic>;
287*4882a593Smuzhiyun		clocks = <&pmic_osc>;
288*4882a593Smuzhiyun		clock-names = "osc";
289*4882a593Smuzhiyun		#clock-cells = <0>;
290*4882a593Smuzhiyun		clock-output-names = "pmic_clk";
291*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
292*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
293*4882a593Smuzhiyun		rohm,reset-snvs-powered;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun		regulators {
296*4882a593Smuzhiyun			buck1_reg: BUCK1 {
297*4882a593Smuzhiyun				regulator-name = "buck1";
298*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
299*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
300*4882a593Smuzhiyun				regulator-boot-on;
301*4882a593Smuzhiyun				regulator-ramp-delay = <1250>;
302*4882a593Smuzhiyun				rohm,dvs-run-voltage = <900000>;
303*4882a593Smuzhiyun				rohm,dvs-idle-voltage = <850000>;
304*4882a593Smuzhiyun				rohm,dvs-suspend-voltage = <800000>;
305*4882a593Smuzhiyun			};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun			buck2_reg: BUCK2 {
308*4882a593Smuzhiyun				regulator-name = "buck2";
309*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
310*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
311*4882a593Smuzhiyun				regulator-boot-on;
312*4882a593Smuzhiyun				regulator-ramp-delay = <1250>;
313*4882a593Smuzhiyun				rohm,dvs-run-voltage = <1000000>;
314*4882a593Smuzhiyun				rohm,dvs-idle-voltage = <900000>;
315*4882a593Smuzhiyun			};
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun			buck3_reg: BUCK3 {
318*4882a593Smuzhiyun				regulator-name = "buck3";
319*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
320*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
321*4882a593Smuzhiyun				regulator-boot-on;
322*4882a593Smuzhiyun				rohm,dvs-run-voltage = <900000>;
323*4882a593Smuzhiyun			};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun			buck4_reg: BUCK4 {
326*4882a593Smuzhiyun				regulator-name = "buck4";
327*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
328*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
329*4882a593Smuzhiyun				rohm,dvs-run-voltage = <1000000>;
330*4882a593Smuzhiyun			};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun			buck5_reg: BUCK5 {
333*4882a593Smuzhiyun				regulator-name = "buck5";
334*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
335*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
336*4882a593Smuzhiyun				regulator-boot-on;
337*4882a593Smuzhiyun			};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun			buck6_reg: BUCK6 {
340*4882a593Smuzhiyun				regulator-name = "buck6";
341*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
342*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
343*4882a593Smuzhiyun				regulator-boot-on;
344*4882a593Smuzhiyun			};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun			buck7_reg: BUCK7 {
347*4882a593Smuzhiyun				regulator-name = "buck7";
348*4882a593Smuzhiyun				regulator-min-microvolt = <1605000>;
349*4882a593Smuzhiyun				regulator-max-microvolt = <1995000>;
350*4882a593Smuzhiyun				regulator-boot-on;
351*4882a593Smuzhiyun			};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun			buck8_reg: BUCK8 {
354*4882a593Smuzhiyun				regulator-name = "buck8";
355*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
356*4882a593Smuzhiyun				regulator-max-microvolt = <1400000>;
357*4882a593Smuzhiyun				regulator-boot-on;
358*4882a593Smuzhiyun			};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun			ldo1_reg: LDO1 {
361*4882a593Smuzhiyun				regulator-name = "ldo1";
362*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
363*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
364*4882a593Smuzhiyun				regulator-boot-on;
365*4882a593Smuzhiyun				/* leave on for snvs power button */
366*4882a593Smuzhiyun				regulator-always-on;
367*4882a593Smuzhiyun			};
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun			ldo2_reg: LDO2 {
370*4882a593Smuzhiyun				regulator-name = "ldo2";
371*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
372*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
373*4882a593Smuzhiyun				regulator-boot-on;
374*4882a593Smuzhiyun				/* leave on for snvs power button */
375*4882a593Smuzhiyun				regulator-always-on;
376*4882a593Smuzhiyun			};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun			ldo3_reg: LDO3 {
379*4882a593Smuzhiyun				regulator-name = "ldo3";
380*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
381*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
382*4882a593Smuzhiyun				regulator-boot-on;
383*4882a593Smuzhiyun			};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun			ldo4_reg: LDO4 {
386*4882a593Smuzhiyun				regulator-name = "ldo4";
387*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
388*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
389*4882a593Smuzhiyun				regulator-boot-on;
390*4882a593Smuzhiyun			};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun			ldo5_reg: LDO5 {
393*4882a593Smuzhiyun				regulator-name = "ldo5";
394*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
395*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
396*4882a593Smuzhiyun			};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun			ldo6_reg: LDO6 {
399*4882a593Smuzhiyun				regulator-name = "ldo6";
400*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
401*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
402*4882a593Smuzhiyun				regulator-boot-on;
403*4882a593Smuzhiyun			};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun			ldo7_reg: LDO7 {
406*4882a593Smuzhiyun				regulator-name = "ldo7";
407*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
408*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
409*4882a593Smuzhiyun				regulator-boot-on;
410*4882a593Smuzhiyun			};
411*4882a593Smuzhiyun		};
412*4882a593Smuzhiyun	};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun	typec_ptn5100: usb-typec@52 {
415*4882a593Smuzhiyun		compatible = "nxp,ptn5110";
416*4882a593Smuzhiyun		reg = <0x52>;
417*4882a593Smuzhiyun		pinctrl-names = "default";
418*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_typec>;
419*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
420*4882a593Smuzhiyun		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun		connector {
423*4882a593Smuzhiyun			compatible = "usb-c-connector";
424*4882a593Smuzhiyun			label = "USB-C";
425*4882a593Smuzhiyun			data-role = "dual";
426*4882a593Smuzhiyun			power-role = "dual";
427*4882a593Smuzhiyun			try-power-role = "sink";
428*4882a593Smuzhiyun			source-pdos = <PDO_FIXED(5000, 2000,
429*4882a593Smuzhiyun				PDO_FIXED_USB_COMM |
430*4882a593Smuzhiyun				PDO_FIXED_DUAL_ROLE |
431*4882a593Smuzhiyun				PDO_FIXED_DATA_SWAP )>;
432*4882a593Smuzhiyun			sink-pdos = <PDO_FIXED(5000, 3500, PDO_FIXED_USB_COMM |
433*4882a593Smuzhiyun				PDO_FIXED_DUAL_ROLE |
434*4882a593Smuzhiyun				PDO_FIXED_DATA_SWAP )
435*4882a593Smuzhiyun			     PDO_VAR(5000, 5000, 3500)>;
436*4882a593Smuzhiyun			op-sink-microwatt = <10000000>;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun			ports {
439*4882a593Smuzhiyun				#address-cells = <1>;
440*4882a593Smuzhiyun				#size-cells = <0>;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun				port@0 {
443*4882a593Smuzhiyun					reg = <0>;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun					usb_con_hs: endpoint {
446*4882a593Smuzhiyun						remote-endpoint = <&typec_hs>;
447*4882a593Smuzhiyun					};
448*4882a593Smuzhiyun				};
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun				port@1 {
451*4882a593Smuzhiyun					reg = <1>;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun					usb_con_ss: endpoint {
454*4882a593Smuzhiyun						remote-endpoint = <&typec_ss>;
455*4882a593Smuzhiyun					};
456*4882a593Smuzhiyun				};
457*4882a593Smuzhiyun			};
458*4882a593Smuzhiyun		};
459*4882a593Smuzhiyun	};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun	rtc@68 {
462*4882a593Smuzhiyun		compatible = "microcrystal,rv4162";
463*4882a593Smuzhiyun		reg = <0x68>;
464*4882a593Smuzhiyun		pinctrl-names = "default";
465*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_rtc>;
466*4882a593Smuzhiyun		interrupt-parent = <&gpio4>;
467*4882a593Smuzhiyun		interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
468*4882a593Smuzhiyun	};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun	charger@6b { /* bq25896 */
471*4882a593Smuzhiyun		compatible = "ti,bq25890";
472*4882a593Smuzhiyun		reg = <0x6b>;
473*4882a593Smuzhiyun		pinctrl-names = "default";
474*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_charger>;
475*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
476*4882a593Smuzhiyun		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
477*4882a593Smuzhiyun		ti,battery-regulation-voltage = <4192000>; /* 4.192V */
478*4882a593Smuzhiyun		ti,charge-current = <1600000>; /* 1.6A */
479*4882a593Smuzhiyun		ti,termination-current = <66000>;  /* 66mA */
480*4882a593Smuzhiyun		ti,precharge-current = <130000>; /* 130mA */
481*4882a593Smuzhiyun		ti,minimum-sys-voltage = <3000000>; /* 3V */
482*4882a593Smuzhiyun		ti,boost-voltage = <5000000>; /* 5V */
483*4882a593Smuzhiyun		ti,boost-max-current = <50000>; /* 50mA */
484*4882a593Smuzhiyun	};
485*4882a593Smuzhiyun};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun&i2c3 {
488*4882a593Smuzhiyun	clock-frequency = <100000>;
489*4882a593Smuzhiyun	pinctrl-names = "default";
490*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
491*4882a593Smuzhiyun	status = "okay";
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun	magnetometer@1e	{
494*4882a593Smuzhiyun		compatible = "st,lsm9ds1-magn";
495*4882a593Smuzhiyun		reg = <0x1e>;
496*4882a593Smuzhiyun		pinctrl-names = "default";
497*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_imu>;
498*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
499*4882a593Smuzhiyun		interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
500*4882a593Smuzhiyun		vdd-supply = <&reg_3v3_p>;
501*4882a593Smuzhiyun		vddio-supply = <&reg_3v3_p>;
502*4882a593Smuzhiyun	};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun	sgtl5000: audio-codec@a {
505*4882a593Smuzhiyun		compatible = "fsl,sgtl5000";
506*4882a593Smuzhiyun		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
507*4882a593Smuzhiyun		assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
508*4882a593Smuzhiyun		assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
509*4882a593Smuzhiyun		assigned-clock-rates = <24576000>;
510*4882a593Smuzhiyun		#sound-dai-cells = <0>;
511*4882a593Smuzhiyun		reg = <0x0a>;
512*4882a593Smuzhiyun		VDDD-supply = <&reg_1v8_p>;
513*4882a593Smuzhiyun		VDDIO-supply = <&reg_3v3_p>;
514*4882a593Smuzhiyun		VDDA-supply = <&reg_3v3_p>;
515*4882a593Smuzhiyun	};
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun	touchscreen@5d {
518*4882a593Smuzhiyun		compatible = "goodix,gt5688";
519*4882a593Smuzhiyun		reg = <0x5d>;
520*4882a593Smuzhiyun		pinctrl-names = "default";
521*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_ts>;
522*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
523*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
524*4882a593Smuzhiyun		reset-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
525*4882a593Smuzhiyun		irq-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
526*4882a593Smuzhiyun		touchscreen-size-x = <720>;
527*4882a593Smuzhiyun		touchscreen-size-y = <1440>;
528*4882a593Smuzhiyun		AVDD28-supply = <&reg_2v8_p>;
529*4882a593Smuzhiyun		VDDIO-supply = <&reg_1v8_p>;
530*4882a593Smuzhiyun	};
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun	proximity-sensor@60 {
533*4882a593Smuzhiyun		compatible = "vishay,vcnl4040";
534*4882a593Smuzhiyun		reg = <0x60>;
535*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_prox>;
536*4882a593Smuzhiyun	};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun	accel-gyro@6a {
539*4882a593Smuzhiyun		compatible = "st,lsm9ds1-imu";
540*4882a593Smuzhiyun		reg = <0x6a>;
541*4882a593Smuzhiyun		vdd-supply = <&reg_3v3_p>;
542*4882a593Smuzhiyun		vddio-supply = <&reg_3v3_p>;
543*4882a593Smuzhiyun		mount-matrix =  "1",  "0",  "0",
544*4882a593Smuzhiyun				"0",  "1",  "0",
545*4882a593Smuzhiyun				"0",  "0", "-1";
546*4882a593Smuzhiyun	};
547*4882a593Smuzhiyun};
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun&iomuxc {
550*4882a593Smuzhiyun	pinctrl_bl: blgrp {
551*4882a593Smuzhiyun		fsl,pins = <
552*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT	0x6 /* DSI_BL_PWM */
553*4882a593Smuzhiyun		>;
554*4882a593Smuzhiyun	};
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun	pinctrl_bt: btgrp {
557*4882a593Smuzhiyun		fsl,pins = <
558*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11	0x16 /* nBT_DISABLE */
559*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7	0x10 /* BT_HOST_WAKE */
560*4882a593Smuzhiyun		>;
561*4882a593Smuzhiyun	};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun	pinctrl_charger: chargergrp {
564*4882a593Smuzhiyun		fsl,pins = <
565*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25	0x80 /* CHRG_nINT */
566*4882a593Smuzhiyun		>;
567*4882a593Smuzhiyun	};
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun	pinctrl_fec1: fec1grp {
570*4882a593Smuzhiyun		fsl,pins = <
571*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC			0x3
572*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
573*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
574*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
575*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
576*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
577*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
578*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
579*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
580*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
581*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
582*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
583*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
584*4882a593Smuzhiyun			MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
585*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
586*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2      0x1f
587*4882a593Smuzhiyun		>;
588*4882a593Smuzhiyun	};
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun	pinctrl_ts: tsgrp {
591*4882a593Smuzhiyun		fsl,pins = <
592*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0		0x16  /* TOUCH INT */
593*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5	0x19  /* TOUCH RST */
594*4882a593Smuzhiyun		>;
595*4882a593Smuzhiyun	};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun	pinctrl_gpio_leds: gpioledgrp {
598*4882a593Smuzhiyun		fsl,pins = <
599*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x16
600*4882a593Smuzhiyun		>;
601*4882a593Smuzhiyun	};
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun	pinctrl_gpio_keys: gpiokeygrp {
604*4882a593Smuzhiyun		fsl,pins = <
605*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21	0x16
606*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22	0x16
607*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x180  /* HP_DET */
608*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80   /* nWoWWAN */
609*4882a593Smuzhiyun		>;
610*4882a593Smuzhiyun	};
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun	pinctrl_haptic: hapticgrp {
613*4882a593Smuzhiyun		fsl,pins = <
614*4882a593Smuzhiyun			MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4		0xc6   /* nHAPTIC */
615*4882a593Smuzhiyun		>;
616*4882a593Smuzhiyun	};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
619*4882a593Smuzhiyun		fsl,pins = <
620*4882a593Smuzhiyun			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL		0x4000001f
621*4882a593Smuzhiyun			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA		0x4000001f
622*4882a593Smuzhiyun		>;
623*4882a593Smuzhiyun	};
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
626*4882a593Smuzhiyun		fsl,pins = <
627*4882a593Smuzhiyun			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000001f
628*4882a593Smuzhiyun			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000001f
629*4882a593Smuzhiyun		>;
630*4882a593Smuzhiyun	};
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun	pinctrl_imu: imugrp {
633*4882a593Smuzhiyun		fsl,pins = <
634*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19	0x8  /* IMU_INT */
635*4882a593Smuzhiyun		>;
636*4882a593Smuzhiyun	};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun	pinctrl_pmic: pmicgrp {
639*4882a593Smuzhiyun		fsl,pins = <
640*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x80  /* PMIC intr */
641*4882a593Smuzhiyun		>;
642*4882a593Smuzhiyun	};
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun	pinctrl_prox: proxgrp {
645*4882a593Smuzhiyun		fsl,pins = <
646*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x80  /* prox intr */
647*4882a593Smuzhiyun		>;
648*4882a593Smuzhiyun	};
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun	pinctrl_pwr_en: pwrengrp {
651*4882a593Smuzhiyun		fsl,pins = <
652*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x06
653*4882a593Smuzhiyun		>;
654*4882a593Smuzhiyun	};
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun	pinctrl_rtc: rtcgrp {
657*4882a593Smuzhiyun		fsl,pins = <
658*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29	0x80  /* RTC intr */
659*4882a593Smuzhiyun		>;
660*4882a593Smuzhiyun	};
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun	pinctrl_sai2: sai2grp {
663*4882a593Smuzhiyun		fsl,pins = <
664*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
665*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
666*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
667*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
668*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
669*4882a593Smuzhiyun		>;
670*4882a593Smuzhiyun	};
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun	pinctrl_sai6: sai6grp {
673*4882a593Smuzhiyun		fsl,pins = <
674*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0	0xd6
675*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC	0xd6
676*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK     0xd6
677*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0	0xd6
678*4882a593Smuzhiyun		>;
679*4882a593Smuzhiyun	};
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun	pinctrl_typec: typecgrp {
682*4882a593Smuzhiyun		fsl,pins = <
683*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12		0x16
684*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1		0x80
685*4882a593Smuzhiyun		>;
686*4882a593Smuzhiyun	};
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun	pinctrl_uart1: uart1grp {
689*4882a593Smuzhiyun		fsl,pins = <
690*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
691*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x49
692*4882a593Smuzhiyun		>;
693*4882a593Smuzhiyun	};
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
696*4882a593Smuzhiyun		fsl,pins = <
697*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
698*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
699*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B		0x49
700*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B		0x49
701*4882a593Smuzhiyun		>;
702*4882a593Smuzhiyun	};
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
705*4882a593Smuzhiyun		fsl,pins = <
706*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
707*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
708*4882a593Smuzhiyun		>;
709*4882a593Smuzhiyun	};
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun	pinctrl_uart4: uart4grp {
712*4882a593Smuzhiyun		fsl,pins = <
713*4882a593Smuzhiyun			MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX		0x49
714*4882a593Smuzhiyun			MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX		0x49
715*4882a593Smuzhiyun			MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B	0x49
716*4882a593Smuzhiyun			MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B		0x49
717*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x49
718*4882a593Smuzhiyun		>;
719*4882a593Smuzhiyun	};
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun	pinctrl_usdhc1: usdhc1grp {
722*4882a593Smuzhiyun		fsl,pins = <
723*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
724*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
725*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
726*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
727*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
728*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
729*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
730*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
731*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
732*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
733*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x83
734*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
735*4882a593Smuzhiyun		>;
736*4882a593Smuzhiyun	};
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
739*4882a593Smuzhiyun		fsl,pins = <
740*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
741*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
742*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
743*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
744*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
745*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
746*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
747*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
748*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
749*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
750*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x8d
751*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
752*4882a593Smuzhiyun		>;
753*4882a593Smuzhiyun	};
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
756*4882a593Smuzhiyun		fsl,pins = <
757*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
758*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
759*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
760*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
761*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
762*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
763*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
764*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
765*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
766*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
767*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x9f
768*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
769*4882a593Smuzhiyun		>;
770*4882a593Smuzhiyun	};
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun	pinctrl_usdhc2_pwr: usdhc2pwrgrp {
773*4882a593Smuzhiyun		fsl,pins = <
774*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
775*4882a593Smuzhiyun		>;
776*4882a593Smuzhiyun	};
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
779*4882a593Smuzhiyun		fsl,pins = <
780*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20		0x80 /* WIFI_WAKE */
781*4882a593Smuzhiyun		>;
782*4882a593Smuzhiyun	};
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
785*4882a593Smuzhiyun		fsl,pins = <
786*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83
787*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3
788*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xc3
789*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xc3
790*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xc3
791*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xc3
792*4882a593Smuzhiyun		>;
793*4882a593Smuzhiyun	};
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
796*4882a593Smuzhiyun		fsl,pins = <
797*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x8d
798*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcd
799*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcd
800*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcd
801*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcd
802*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcd
803*4882a593Smuzhiyun		>;
804*4882a593Smuzhiyun	};
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
807*4882a593Smuzhiyun		fsl,pins = <
808*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f
809*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xcf
810*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0	0xcf
811*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1	0xcf
812*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2	0xcf
813*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3	0xcf
814*4882a593Smuzhiyun		>;
815*4882a593Smuzhiyun	};
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun	pinctrl_wdog: wdoggrp {
818*4882a593Smuzhiyun		fsl,pins = <
819*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
820*4882a593Smuzhiyun		>;
821*4882a593Smuzhiyun	};
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun	pinctrl_wifi_pwr_en: wifipwrengrp {
824*4882a593Smuzhiyun		fsl,pins = <
825*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5         0x06
826*4882a593Smuzhiyun		>;
827*4882a593Smuzhiyun	};
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun	pinctrl_wwan: wwangrp {
830*4882a593Smuzhiyun		fsl,pins = <
831*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4	0x09 /* nWWAN_DISABLE */
832*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8	0x80 /* nWoWWAN */
833*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
834*4882a593Smuzhiyun		>;
835*4882a593Smuzhiyun	};
836*4882a593Smuzhiyun};
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun&lcdif {
839*4882a593Smuzhiyun	status = "okay";
840*4882a593Smuzhiyun};
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun&mipi_dsi {
843*4882a593Smuzhiyun	status = "okay";
844*4882a593Smuzhiyun	#address-cells = <1>;
845*4882a593Smuzhiyun	#size-cells = <0>;
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun	panel@0 {
848*4882a593Smuzhiyun		compatible = "rocktech,jh057n00900";
849*4882a593Smuzhiyun		reg = <0>;
850*4882a593Smuzhiyun		backlight = <&backlight_dsi>;
851*4882a593Smuzhiyun		reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
852*4882a593Smuzhiyun		iovcc-supply = <&reg_1v8_p>;
853*4882a593Smuzhiyun		vcc-supply = <&reg_2v8_p>;
854*4882a593Smuzhiyun		port {
855*4882a593Smuzhiyun			panel_in: endpoint {
856*4882a593Smuzhiyun				remote-endpoint = <&mipi_dsi_out>;
857*4882a593Smuzhiyun			};
858*4882a593Smuzhiyun		};
859*4882a593Smuzhiyun	};
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun	ports {
862*4882a593Smuzhiyun		port@1 {
863*4882a593Smuzhiyun			reg = <1>;
864*4882a593Smuzhiyun			mipi_dsi_out: endpoint {
865*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
866*4882a593Smuzhiyun			};
867*4882a593Smuzhiyun		};
868*4882a593Smuzhiyun	};
869*4882a593Smuzhiyun};
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun&pgc_gpu {
872*4882a593Smuzhiyun	power-supply = <&buck3_reg>;
873*4882a593Smuzhiyun};
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun&pgc_vpu {
876*4882a593Smuzhiyun	power-supply = <&buck4_reg>;
877*4882a593Smuzhiyun};
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun&pwm1 {
880*4882a593Smuzhiyun	pinctrl-names = "default";
881*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_bl>;
882*4882a593Smuzhiyun	status = "okay";
883*4882a593Smuzhiyun};
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun&snvs_pwrkey {
886*4882a593Smuzhiyun	status = "okay";
887*4882a593Smuzhiyun};
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun&sai2 {
890*4882a593Smuzhiyun	pinctrl-names = "default";
891*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sai2>;
892*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
893*4882a593Smuzhiyun	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
894*4882a593Smuzhiyun	assigned-clock-rates = <24576000>;
895*4882a593Smuzhiyun	status = "okay";
896*4882a593Smuzhiyun};
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun&sai6 {
899*4882a593Smuzhiyun	pinctrl-names = "default";
900*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sai6>;
901*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MQ_CLK_SAI6>;
902*4882a593Smuzhiyun	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
903*4882a593Smuzhiyun	assigned-clock-rates = <24576000>;
904*4882a593Smuzhiyun	fsl,sai-synchronous-rx;
905*4882a593Smuzhiyun	status = "okay";
906*4882a593Smuzhiyun};
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun&uart1 { /* console */
909*4882a593Smuzhiyun	pinctrl-names = "default";
910*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart1>;
911*4882a593Smuzhiyun	status = "okay";
912*4882a593Smuzhiyun};
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun&uart3 { /* GNSS */
915*4882a593Smuzhiyun	pinctrl-names = "default";
916*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
917*4882a593Smuzhiyun	status = "okay";
918*4882a593Smuzhiyun};
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun&uart4 { /* BT */
921*4882a593Smuzhiyun	pinctrl-names = "default";
922*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
923*4882a593Smuzhiyun	uart-has-rtscts;
924*4882a593Smuzhiyun	status = "okay";
925*4882a593Smuzhiyun};
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun&usb3_phy0 {
928*4882a593Smuzhiyun	vbus-supply = <&reg_5v_p>;
929*4882a593Smuzhiyun	status = "okay";
930*4882a593Smuzhiyun};
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun&usb3_phy1 {
933*4882a593Smuzhiyun	vbus-supply = <&reg_5v_p>;
934*4882a593Smuzhiyun	status = "okay";
935*4882a593Smuzhiyun};
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun&usb_dwc3_0 {
938*4882a593Smuzhiyun	#address-cells = <1>;
939*4882a593Smuzhiyun	#size-cells = <0>;
940*4882a593Smuzhiyun	dr_mode = "otg";
941*4882a593Smuzhiyun	status = "okay";
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun	port@0 {
944*4882a593Smuzhiyun		reg = <0>;
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun		typec_hs: endpoint {
947*4882a593Smuzhiyun			remote-endpoint = <&usb_con_hs>;
948*4882a593Smuzhiyun		};
949*4882a593Smuzhiyun	};
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun	port@1 {
952*4882a593Smuzhiyun		reg = <1>;
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun		typec_ss: endpoint {
955*4882a593Smuzhiyun			remote-endpoint = <&usb_con_ss>;
956*4882a593Smuzhiyun		};
957*4882a593Smuzhiyun	};
958*4882a593Smuzhiyun};
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun&usb_dwc3_1 {
961*4882a593Smuzhiyun	dr_mode = "host";
962*4882a593Smuzhiyun	status = "okay";
963*4882a593Smuzhiyun};
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun&usdhc1 {
966*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
967*4882a593Smuzhiyun	assigned-clock-rates = <400000000>;
968*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
969*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc1>;
970*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
971*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
972*4882a593Smuzhiyun	bus-width = <8>;
973*4882a593Smuzhiyun	non-removable;
974*4882a593Smuzhiyun	status = "okay";
975*4882a593Smuzhiyun};
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun&usdhc2 {
978*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
979*4882a593Smuzhiyun	assigned-clock-rates = <200000000>;
980*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
981*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>;
982*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
983*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
984*4882a593Smuzhiyun	bus-width = <4>;
985*4882a593Smuzhiyun	vmmc-supply = <&reg_usdhc2_vmmc>;
986*4882a593Smuzhiyun	power-supply = <&wifi_pwr_en>;
987*4882a593Smuzhiyun	broken-cd;
988*4882a593Smuzhiyun	disable-wp;
989*4882a593Smuzhiyun	cap-sdio-irq;
990*4882a593Smuzhiyun	keep-power-in-suspend;
991*4882a593Smuzhiyun	wakeup-source;
992*4882a593Smuzhiyun	status = "okay";
993*4882a593Smuzhiyun};
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun&wdog1 {
996*4882a593Smuzhiyun	pinctrl-names = "default";
997*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_wdog>;
998*4882a593Smuzhiyun	fsl,ext-reset-output;
999*4882a593Smuzhiyun	status = "okay";
1000*4882a593Smuzhiyun};
1001