xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
9*4882a593Smuzhiyun#include "imx8mq-sr-som.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "SolidRun i.MX8MQ HummingBoard Pulse";
13*4882a593Smuzhiyun	compatible = "solidrun,hummingboard-pulse", "fsl,imx8mq";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	chosen {
16*4882a593Smuzhiyun		stdout-path = &uart1;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
20*4882a593Smuzhiyun		compatible = "regulator-fixed";
21*4882a593Smuzhiyun		pinctrl-names = "default";
22*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
23*4882a593Smuzhiyun		regulator-name = "VSD_3V3";
24*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
25*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
26*4882a593Smuzhiyun		gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	reg_v_5v0: regulator-v-5v0 {
30*4882a593Smuzhiyun		compatible = "regulator-fixed";
31*4882a593Smuzhiyun		regulator-name = "v_5v0";
32*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
33*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
34*4882a593Smuzhiyun		regulator-always-on;
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun&i2c2 {
39*4882a593Smuzhiyun	pinctrl-names = "default";
40*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
41*4882a593Smuzhiyun	clock-frequency = <100000>;
42*4882a593Smuzhiyun	status = "okay";
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	typec_ptn5100: usb-typec@50 {
45*4882a593Smuzhiyun		compatible = "nxp,ptn5110";
46*4882a593Smuzhiyun		reg = <0x50>;
47*4882a593Smuzhiyun		pinctrl-names = "default";
48*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_typec>;
49*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
50*4882a593Smuzhiyun		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		connector {
53*4882a593Smuzhiyun			compatible = "usb-c-connector";
54*4882a593Smuzhiyun			label = "USB-C";
55*4882a593Smuzhiyun			data-role = "dual";
56*4882a593Smuzhiyun			power-role = "dual";
57*4882a593Smuzhiyun			try-power-role = "sink";
58*4882a593Smuzhiyun			source-pdos = <PDO_FIXED(5000, 2000,
59*4882a593Smuzhiyun						 PDO_FIXED_USB_COMM |
60*4882a593Smuzhiyun						 PDO_FIXED_SUSPEND |
61*4882a593Smuzhiyun						 PDO_FIXED_EXTPOWER)>;
62*4882a593Smuzhiyun			sink-pdos = <PDO_FIXED(5000, 2000,
63*4882a593Smuzhiyun					       PDO_FIXED_USB_COMM |
64*4882a593Smuzhiyun					       PDO_FIXED_SUSPEND |
65*4882a593Smuzhiyun					       PDO_FIXED_EXTPOWER)
66*4882a593Smuzhiyun				     PDO_FIXED(9000, 2000,
67*4882a593Smuzhiyun					       PDO_FIXED_USB_COMM |
68*4882a593Smuzhiyun					       PDO_FIXED_SUSPEND |
69*4882a593Smuzhiyun					       PDO_FIXED_EXTPOWER)>;
70*4882a593Smuzhiyun			op-sink-microwatt = <9000000>;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun			port {
73*4882a593Smuzhiyun				typec1_dr_sw: endpoint {
74*4882a593Smuzhiyun					remote-endpoint = <&usb1_drd_sw>;
75*4882a593Smuzhiyun				};
76*4882a593Smuzhiyun			};
77*4882a593Smuzhiyun		};
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun&i2c3 {
82*4882a593Smuzhiyun	pinctrl-names = "default";
83*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
84*4882a593Smuzhiyun	clock-frequency = <100000>;
85*4882a593Smuzhiyun	status = "okay";
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	eeprom@57 {
88*4882a593Smuzhiyun		compatible = "atmel,24c02";
89*4882a593Smuzhiyun		reg = <0x57>;
90*4882a593Smuzhiyun		status = "okay";
91*4882a593Smuzhiyun	};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun	rtc@69 {
94*4882a593Smuzhiyun		compatible = "abracon,ab1805";
95*4882a593Smuzhiyun		reg = <0x69>;
96*4882a593Smuzhiyun		abracon,tc-diode = "schottky";
97*4882a593Smuzhiyun		abracon,tc-resistor = <3>;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun&uart2 { /* J35 header */
102*4882a593Smuzhiyun	pinctrl-names = "default";
103*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
104*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
105*4882a593Smuzhiyun	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
106*4882a593Smuzhiyun	status = "okay";
107*4882a593Smuzhiyun};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun&uart3 { /* Mikrobus */
110*4882a593Smuzhiyun	pinctrl-names = "default";
111*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart3>;
112*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
113*4882a593Smuzhiyun	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
114*4882a593Smuzhiyun	uart-has-rtscts;
115*4882a593Smuzhiyun	status = "okay";
116*4882a593Smuzhiyun};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun&usdhc2 {
119*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
120*4882a593Smuzhiyun	assigned-clock-rates = <200000000>;
121*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
122*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
123*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
124*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
125*4882a593Smuzhiyun	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
126*4882a593Smuzhiyun	vmmc-supply = <&reg_usdhc2_vmmc>;
127*4882a593Smuzhiyun	status = "okay";
128*4882a593Smuzhiyun};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun&usb_dwc3_0 {
131*4882a593Smuzhiyun	dr_mode = "otg";
132*4882a593Smuzhiyun	status = "okay";
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	port {
135*4882a593Smuzhiyun		usb1_drd_sw: endpoint {
136*4882a593Smuzhiyun			remote-endpoint = <&typec1_dr_sw>;
137*4882a593Smuzhiyun		};
138*4882a593Smuzhiyun	};
139*4882a593Smuzhiyun};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun&usb_dwc3_1 {
142*4882a593Smuzhiyun	dr_mode = "host";
143*4882a593Smuzhiyun	status = "okay";
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&usb3_phy0 {
147*4882a593Smuzhiyun	status = "okay";
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&usb3_phy1 {
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&iomuxc {
155*4882a593Smuzhiyun	pinctrl-names = "default";
156*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_hog>;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun	pinctrl_hog: hoggrp {
159*4882a593Smuzhiyun		fsl,pins = <
160*4882a593Smuzhiyun			/* MikroBus Analog */
161*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x41
162*4882a593Smuzhiyun			/* MikroBus Reset */
163*4882a593Smuzhiyun			MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23		0x41
164*4882a593Smuzhiyun			/*
165*4882a593Smuzhiyun			 * The following 2 pins need to be commented out and
166*4882a593Smuzhiyun			 * reconfigured to enable RTS/CTS on UART3
167*4882a593Smuzhiyun			 */
168*4882a593Smuzhiyun			/* MikroBus PWM */
169*4882a593Smuzhiyun			MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8		0x41
170*4882a593Smuzhiyun			/* MikroBus INT */
171*4882a593Smuzhiyun			MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x41
172*4882a593Smuzhiyun		>;
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
176*4882a593Smuzhiyun		fsl,pins = <
177*4882a593Smuzhiyun			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL		0x4000007f
178*4882a593Smuzhiyun			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA		0x4000007f
179*4882a593Smuzhiyun		>;
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
183*4882a593Smuzhiyun		fsl,pins = <
184*4882a593Smuzhiyun			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x4000007f
185*4882a593Smuzhiyun			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x4000007f
186*4882a593Smuzhiyun		>;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	pinctrl_typec: typecgrp {
190*4882a593Smuzhiyun		fsl,pins = <
191*4882a593Smuzhiyun			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15	0x16
192*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x17059
193*4882a593Smuzhiyun		>;
194*4882a593Smuzhiyun	};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
197*4882a593Smuzhiyun		fsl,pins = <
198*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x49
199*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x49
200*4882a593Smuzhiyun		>;
201*4882a593Smuzhiyun	};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun	pinctrl_uart3: uart3grp {
204*4882a593Smuzhiyun		fsl,pins = <
205*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
206*4882a593Smuzhiyun			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
207*4882a593Smuzhiyun			/*
208*4882a593Smuzhiyun			 * These pins are by default GPIO on the Mikro Bus
209*4882a593Smuzhiyun			 * Header. To use RTS/CTS on UART3 comment them out
210*4882a593Smuzhiyun			 * of the hoggrp and enable them here
211*4882a593Smuzhiyun			 */
212*4882a593Smuzhiyun			/* MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x49 */
213*4882a593Smuzhiyun			/* MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B	0x49 */
214*4882a593Smuzhiyun		>;
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
218*4882a593Smuzhiyun		fsl,pins = <
219*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12	0x41
220*4882a593Smuzhiyun		>;
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	pinctrl_usdhc2_vmmc: usdhc2vmmcgpiogrp {
224*4882a593Smuzhiyun		fsl,pins = <
225*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13	0x41
226*4882a593Smuzhiyun		>;
227*4882a593Smuzhiyun	};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
230*4882a593Smuzhiyun		fsl,pins = <
231*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
232*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
233*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
234*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
235*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
236*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
237*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
238*4882a593Smuzhiyun		>;
239*4882a593Smuzhiyun	};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
242*4882a593Smuzhiyun		fsl,pins = <
243*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
244*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
245*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
246*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
247*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
248*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
249*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
250*4882a593Smuzhiyun		>;
251*4882a593Smuzhiyun	};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
254*4882a593Smuzhiyun		fsl,pins = <
255*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
256*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
257*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
258*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
259*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
260*4882a593Smuzhiyun			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
261*4882a593Smuzhiyun			MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT		0xc1
262*4882a593Smuzhiyun		>;
263*4882a593Smuzhiyun	};
264*4882a593Smuzhiyun};
265