xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2020 NXP
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/usb/pd.h>
9*4882a593Smuzhiyun#include "imx8mm.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	chosen {
13*4882a593Smuzhiyun		stdout-path = &uart2;
14*4882a593Smuzhiyun	};
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	memory@40000000 {
17*4882a593Smuzhiyun		device_type = "memory";
18*4882a593Smuzhiyun		reg = <0x0 0x40000000 0 0x80000000>;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	leds {
22*4882a593Smuzhiyun		compatible = "gpio-leds";
23*4882a593Smuzhiyun		pinctrl-names = "default";
24*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_led>;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		status {
27*4882a593Smuzhiyun			label = "status";
28*4882a593Smuzhiyun			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
29*4882a593Smuzhiyun			default-state = "on";
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	reg_usdhc2_vmmc: regulator-usdhc2 {
34*4882a593Smuzhiyun		compatible = "regulator-fixed";
35*4882a593Smuzhiyun		pinctrl-names = "default";
36*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
37*4882a593Smuzhiyun		regulator-name = "VSD_3V3";
38*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
39*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
40*4882a593Smuzhiyun		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41*4882a593Smuzhiyun		enable-active-high;
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	wm8524: audio-codec {
45*4882a593Smuzhiyun		#sound-dai-cells = <0>;
46*4882a593Smuzhiyun		compatible = "wlf,wm8524";
47*4882a593Smuzhiyun		pinctrl-names = "default";
48*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_gpio_wlf>;
49*4882a593Smuzhiyun		wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	sound-wm8524 {
53*4882a593Smuzhiyun		compatible = "simple-audio-card";
54*4882a593Smuzhiyun		simple-audio-card,name = "wm8524-audio";
55*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
56*4882a593Smuzhiyun		simple-audio-card,frame-master = <&cpudai>;
57*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&cpudai>;
58*4882a593Smuzhiyun		simple-audio-card,widgets =
59*4882a593Smuzhiyun			"Line", "Left Line Out Jack",
60*4882a593Smuzhiyun			"Line", "Right Line Out Jack";
61*4882a593Smuzhiyun		simple-audio-card,routing =
62*4882a593Smuzhiyun			"Left Line Out Jack", "LINEVOUTL",
63*4882a593Smuzhiyun			"Right Line Out Jack", "LINEVOUTR";
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		cpudai: simple-audio-card,cpu {
66*4882a593Smuzhiyun			sound-dai = <&sai3>;
67*4882a593Smuzhiyun			dai-tdm-slot-num = <2>;
68*4882a593Smuzhiyun			dai-tdm-slot-width = <32>;
69*4882a593Smuzhiyun		};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun		simple-audio-card,codec {
72*4882a593Smuzhiyun			sound-dai = <&wm8524>;
73*4882a593Smuzhiyun			clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun&A53_0 {
79*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun&A53_1 {
83*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
84*4882a593Smuzhiyun};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun&A53_2 {
87*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&A53_3 {
91*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
92*4882a593Smuzhiyun};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun&fec1 {
95*4882a593Smuzhiyun	pinctrl-names = "default";
96*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_fec1>;
97*4882a593Smuzhiyun	phy-mode = "rgmii-id";
98*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
99*4882a593Smuzhiyun	fsl,magic-packet;
100*4882a593Smuzhiyun	status = "okay";
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	mdio {
103*4882a593Smuzhiyun		#address-cells = <1>;
104*4882a593Smuzhiyun		#size-cells = <0>;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun		ethphy0: ethernet-phy@0 {
107*4882a593Smuzhiyun			compatible = "ethernet-phy-ieee802.3-c22";
108*4882a593Smuzhiyun			reg = <0>;
109*4882a593Smuzhiyun			reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
110*4882a593Smuzhiyun			reset-assert-us = <10000>;
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun&i2c1 {
116*4882a593Smuzhiyun	clock-frequency = <400000>;
117*4882a593Smuzhiyun	pinctrl-names = "default";
118*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1>;
119*4882a593Smuzhiyun	status = "okay";
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	pmic@4b {
122*4882a593Smuzhiyun		compatible = "rohm,bd71847";
123*4882a593Smuzhiyun		reg = <0x4b>;
124*4882a593Smuzhiyun		pinctrl-names = "default";
125*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_pmic>;
126*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
127*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
128*4882a593Smuzhiyun		rohm,reset-snvs-powered;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun		#clock-cells = <0>;
131*4882a593Smuzhiyun		clocks = <&osc_32k 0>;
132*4882a593Smuzhiyun		clock-output-names = "clk-32k-out";
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun		regulators {
135*4882a593Smuzhiyun			buck1_reg: BUCK1 {
136*4882a593Smuzhiyun				regulator-name = "buck1";
137*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
138*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
139*4882a593Smuzhiyun				regulator-boot-on;
140*4882a593Smuzhiyun				regulator-always-on;
141*4882a593Smuzhiyun				regulator-ramp-delay = <1250>;
142*4882a593Smuzhiyun			};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun			buck2_reg: BUCK2 {
145*4882a593Smuzhiyun				regulator-name = "buck2";
146*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
147*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
148*4882a593Smuzhiyun				regulator-boot-on;
149*4882a593Smuzhiyun				regulator-always-on;
150*4882a593Smuzhiyun				regulator-ramp-delay = <1250>;
151*4882a593Smuzhiyun				rohm,dvs-run-voltage = <1000000>;
152*4882a593Smuzhiyun				rohm,dvs-idle-voltage = <900000>;
153*4882a593Smuzhiyun			};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun			buck3_reg: BUCK3 {
156*4882a593Smuzhiyun				// BUCK5 in datasheet
157*4882a593Smuzhiyun				regulator-name = "buck3";
158*4882a593Smuzhiyun				regulator-min-microvolt = <700000>;
159*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
160*4882a593Smuzhiyun				regulator-boot-on;
161*4882a593Smuzhiyun				regulator-always-on;
162*4882a593Smuzhiyun			};
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun			buck4_reg: BUCK4 {
165*4882a593Smuzhiyun				// BUCK6 in datasheet
166*4882a593Smuzhiyun				regulator-name = "buck4";
167*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
168*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
169*4882a593Smuzhiyun				regulator-boot-on;
170*4882a593Smuzhiyun				regulator-always-on;
171*4882a593Smuzhiyun			};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun			buck5_reg: BUCK5 {
174*4882a593Smuzhiyun				// BUCK7 in datasheet
175*4882a593Smuzhiyun				regulator-name = "buck5";
176*4882a593Smuzhiyun				regulator-min-microvolt = <1605000>;
177*4882a593Smuzhiyun				regulator-max-microvolt = <1995000>;
178*4882a593Smuzhiyun				regulator-boot-on;
179*4882a593Smuzhiyun				regulator-always-on;
180*4882a593Smuzhiyun			};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun			buck6_reg: BUCK6 {
183*4882a593Smuzhiyun				// BUCK8 in datasheet
184*4882a593Smuzhiyun				regulator-name = "buck6";
185*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
186*4882a593Smuzhiyun				regulator-max-microvolt = <1400000>;
187*4882a593Smuzhiyun				regulator-boot-on;
188*4882a593Smuzhiyun				regulator-always-on;
189*4882a593Smuzhiyun			};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun			ldo1_reg: LDO1 {
192*4882a593Smuzhiyun				regulator-name = "ldo1";
193*4882a593Smuzhiyun				regulator-min-microvolt = <1600000>;
194*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
195*4882a593Smuzhiyun				regulator-boot-on;
196*4882a593Smuzhiyun				regulator-always-on;
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun			ldo2_reg: LDO2 {
200*4882a593Smuzhiyun				regulator-name = "ldo2";
201*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
202*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
203*4882a593Smuzhiyun				regulator-boot-on;
204*4882a593Smuzhiyun				regulator-always-on;
205*4882a593Smuzhiyun			};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun			ldo3_reg: LDO3 {
208*4882a593Smuzhiyun				regulator-name = "ldo3";
209*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
210*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
211*4882a593Smuzhiyun				regulator-boot-on;
212*4882a593Smuzhiyun				regulator-always-on;
213*4882a593Smuzhiyun			};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun			ldo4_reg: LDO4 {
216*4882a593Smuzhiyun				regulator-name = "ldo4";
217*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
218*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
219*4882a593Smuzhiyun				regulator-boot-on;
220*4882a593Smuzhiyun				regulator-always-on;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun			ldo6_reg: LDO6 {
224*4882a593Smuzhiyun				regulator-name = "ldo6";
225*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
226*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
227*4882a593Smuzhiyun				regulator-boot-on;
228*4882a593Smuzhiyun				regulator-always-on;
229*4882a593Smuzhiyun			};
230*4882a593Smuzhiyun		};
231*4882a593Smuzhiyun	};
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&i2c2 {
235*4882a593Smuzhiyun	clock-frequency = <400000>;
236*4882a593Smuzhiyun	pinctrl-names = "default";
237*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c2>;
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun	ptn5110: tcpc@50 {
241*4882a593Smuzhiyun		compatible = "nxp,ptn5110";
242*4882a593Smuzhiyun		pinctrl-names = "default";
243*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_typec1>;
244*4882a593Smuzhiyun		reg = <0x50>;
245*4882a593Smuzhiyun		interrupt-parent = <&gpio2>;
246*4882a593Smuzhiyun		interrupts = <11 8>;
247*4882a593Smuzhiyun		status = "okay";
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun		port {
250*4882a593Smuzhiyun			typec1_dr_sw: endpoint {
251*4882a593Smuzhiyun				remote-endpoint = <&usb1_drd_sw>;
252*4882a593Smuzhiyun			};
253*4882a593Smuzhiyun		};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun		typec1_con: connector {
256*4882a593Smuzhiyun			compatible = "usb-c-connector";
257*4882a593Smuzhiyun			label = "USB-C";
258*4882a593Smuzhiyun			power-role = "dual";
259*4882a593Smuzhiyun			data-role = "dual";
260*4882a593Smuzhiyun			try-power-role = "sink";
261*4882a593Smuzhiyun			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
262*4882a593Smuzhiyun			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
263*4882a593Smuzhiyun				     PDO_VAR(5000, 20000, 3000)>;
264*4882a593Smuzhiyun			op-sink-microwatt = <15000000>;
265*4882a593Smuzhiyun			self-powered;
266*4882a593Smuzhiyun		};
267*4882a593Smuzhiyun	};
268*4882a593Smuzhiyun};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun&i2c3 {
271*4882a593Smuzhiyun	clock-frequency = <400000>;
272*4882a593Smuzhiyun	pinctrl-names = "default";
273*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c3>;
274*4882a593Smuzhiyun	status = "okay";
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun	pca6416: gpio@20 {
277*4882a593Smuzhiyun		compatible = "ti,tca6416";
278*4882a593Smuzhiyun		reg = <0x20>;
279*4882a593Smuzhiyun		gpio-controller;
280*4882a593Smuzhiyun		#gpio-cells = <2>;
281*4882a593Smuzhiyun	};
282*4882a593Smuzhiyun};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun&sai3 {
285*4882a593Smuzhiyun	pinctrl-names = "default";
286*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_sai3>;
287*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
288*4882a593Smuzhiyun	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
289*4882a593Smuzhiyun	assigned-clock-rates = <24576000>;
290*4882a593Smuzhiyun	status = "okay";
291*4882a593Smuzhiyun};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun&snvs_pwrkey {
294*4882a593Smuzhiyun	status = "okay";
295*4882a593Smuzhiyun};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun&uart2 { /* console */
298*4882a593Smuzhiyun	pinctrl-names = "default";
299*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_uart2>;
300*4882a593Smuzhiyun	status = "okay";
301*4882a593Smuzhiyun};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun&usbotg1 {
304*4882a593Smuzhiyun	dr_mode = "otg";
305*4882a593Smuzhiyun	hnp-disable;
306*4882a593Smuzhiyun	srp-disable;
307*4882a593Smuzhiyun	adp-disable;
308*4882a593Smuzhiyun	usb-role-switch;
309*4882a593Smuzhiyun	samsung,picophy-pre-emp-curr-control = <3>;
310*4882a593Smuzhiyun	samsung,picophy-dc-vol-level-adjust = <7>;
311*4882a593Smuzhiyun	status = "okay";
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun	port {
314*4882a593Smuzhiyun		usb1_drd_sw: endpoint {
315*4882a593Smuzhiyun			remote-endpoint = <&typec1_dr_sw>;
316*4882a593Smuzhiyun		};
317*4882a593Smuzhiyun	};
318*4882a593Smuzhiyun};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun&usdhc2 {
321*4882a593Smuzhiyun	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
322*4882a593Smuzhiyun	assigned-clock-rates = <200000000>;
323*4882a593Smuzhiyun	pinctrl-names = "default", "state_100mhz", "state_200mhz";
324*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
325*4882a593Smuzhiyun	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
326*4882a593Smuzhiyun	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
327*4882a593Smuzhiyun	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
328*4882a593Smuzhiyun	bus-width = <4>;
329*4882a593Smuzhiyun	vmmc-supply = <&reg_usdhc2_vmmc>;
330*4882a593Smuzhiyun	status = "okay";
331*4882a593Smuzhiyun};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun&wdog1 {
334*4882a593Smuzhiyun	pinctrl-names = "default";
335*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_wdog>;
336*4882a593Smuzhiyun	fsl,ext-reset-output;
337*4882a593Smuzhiyun	status = "okay";
338*4882a593Smuzhiyun};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun&iomuxc {
341*4882a593Smuzhiyun	pinctrl_fec1: fec1grp {
342*4882a593Smuzhiyun		fsl,pins = <
343*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
344*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
345*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
346*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
347*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
348*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
349*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
350*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
351*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
352*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
353*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
354*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
355*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
356*4882a593Smuzhiyun			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
357*4882a593Smuzhiyun			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
358*4882a593Smuzhiyun		>;
359*4882a593Smuzhiyun	};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun	pinctrl_gpio_led: gpioledgrp {
362*4882a593Smuzhiyun		fsl,pins = <
363*4882a593Smuzhiyun			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
364*4882a593Smuzhiyun		>;
365*4882a593Smuzhiyun	};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun	pinctrl_gpio_wlf: gpiowlfgrp {
368*4882a593Smuzhiyun		fsl,pins = <
369*4882a593Smuzhiyun			MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21	0xd6
370*4882a593Smuzhiyun		>;
371*4882a593Smuzhiyun	};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun	pinctrl_i2c1: i2c1grp {
374*4882a593Smuzhiyun		fsl,pins = <
375*4882a593Smuzhiyun			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
376*4882a593Smuzhiyun			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
377*4882a593Smuzhiyun		>;
378*4882a593Smuzhiyun	};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun	pinctrl_i2c2: i2c2grp {
381*4882a593Smuzhiyun		fsl,pins = <
382*4882a593Smuzhiyun			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
383*4882a593Smuzhiyun			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
384*4882a593Smuzhiyun		>;
385*4882a593Smuzhiyun	};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun	pinctrl_i2c3: i2c3grp {
388*4882a593Smuzhiyun		fsl,pins = <
389*4882a593Smuzhiyun			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
390*4882a593Smuzhiyun			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
391*4882a593Smuzhiyun		>;
392*4882a593Smuzhiyun	};
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun	pinctrl_pmic: pmicirqgrp {
395*4882a593Smuzhiyun		fsl,pins = <
396*4882a593Smuzhiyun			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141
397*4882a593Smuzhiyun		>;
398*4882a593Smuzhiyun	};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
401*4882a593Smuzhiyun		fsl,pins = <
402*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
403*4882a593Smuzhiyun		>;
404*4882a593Smuzhiyun	};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun	pinctrl_sai3: sai3grp {
407*4882a593Smuzhiyun		fsl,pins = <
408*4882a593Smuzhiyun			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
409*4882a593Smuzhiyun			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
410*4882a593Smuzhiyun			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
411*4882a593Smuzhiyun			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
412*4882a593Smuzhiyun		>;
413*4882a593Smuzhiyun	};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun	pinctrl_typec1: typec1grp {
416*4882a593Smuzhiyun		fsl,pins = <
417*4882a593Smuzhiyun			MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
418*4882a593Smuzhiyun		>;
419*4882a593Smuzhiyun	};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun	pinctrl_uart2: uart2grp {
422*4882a593Smuzhiyun		fsl,pins = <
423*4882a593Smuzhiyun			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
424*4882a593Smuzhiyun			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
425*4882a593Smuzhiyun		>;
426*4882a593Smuzhiyun	};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
429*4882a593Smuzhiyun		fsl,pins = <
430*4882a593Smuzhiyun			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
431*4882a593Smuzhiyun		>;
432*4882a593Smuzhiyun	};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun	pinctrl_usdhc2: usdhc2grp {
435*4882a593Smuzhiyun		fsl,pins = <
436*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
437*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
438*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
439*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
440*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
441*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
442*4882a593Smuzhiyun			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
443*4882a593Smuzhiyun		>;
444*4882a593Smuzhiyun	};
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
447*4882a593Smuzhiyun		fsl,pins = <
448*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
449*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
450*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
451*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
452*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
453*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
454*4882a593Smuzhiyun			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
455*4882a593Smuzhiyun		>;
456*4882a593Smuzhiyun	};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
459*4882a593Smuzhiyun		fsl,pins = <
460*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
461*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
462*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
463*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
464*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
465*4882a593Smuzhiyun			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
466*4882a593Smuzhiyun			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
467*4882a593Smuzhiyun		>;
468*4882a593Smuzhiyun	};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun	pinctrl_wdog: wdoggrp {
471*4882a593Smuzhiyun		fsl,pins = <
472*4882a593Smuzhiyun			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
473*4882a593Smuzhiyun		>;
474*4882a593Smuzhiyun	};
475*4882a593Smuzhiyun};
476