1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2020 NXP 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "imx8mm-evk.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; 12*4882a593Smuzhiyun compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun leds { 15*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpio_led_2>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun status { 18*4882a593Smuzhiyun gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun&gpmi { 24*4882a593Smuzhiyun pinctrl-names = "default"; 25*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_gpmi_nand>; 26*4882a593Smuzhiyun nand-on-flash-bbt; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun}; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun&iomuxc { 31*4882a593Smuzhiyun pinctrl_gpmi_nand: gpmi-nand { 32*4882a593Smuzhiyun fsl,pins = < 33*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 34*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 35*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 36*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 37*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 38*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 39*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 40*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 41*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 42*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 43*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 44*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 45*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 46*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 47*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 48*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 49*4882a593Smuzhiyun >; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun pinctrl_gpio_led_2: gpioled2grp { 53*4882a593Smuzhiyun fsl,pins = < 54*4882a593Smuzhiyun MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 55*4882a593Smuzhiyun >; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun}; 58