1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun// 3*4882a593Smuzhiyun// Device Tree file for LX2160AQDS 4*4882a593Smuzhiyun// 5*4882a593Smuzhiyun// Copyright 2018 NXP 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "fsl-lx2160a.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "NXP Layerscape LX2160AQDS"; 13*4882a593Smuzhiyun compatible = "fsl,lx2160a-qds", "fsl,lx2160a"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun crypto = &crypto; 17*4882a593Smuzhiyun serial0 = &uart0; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun chosen { 21*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun sb_3v3: regulator-sb3v3 { 25*4882a593Smuzhiyun compatible = "regulator-fixed"; 26*4882a593Smuzhiyun regulator-name = "MC34717-3.3VSB"; 27*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 28*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 29*4882a593Smuzhiyun regulator-boot-on; 30*4882a593Smuzhiyun regulator-always-on; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun&crypto { 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun&dspi0 { 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun dflash0: flash@0 { 42*4882a593Smuzhiyun #address-cells = <1>; 43*4882a593Smuzhiyun #size-cells = <1>; 44*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 45*4882a593Smuzhiyun reg = <0>; 46*4882a593Smuzhiyun spi-max-frequency = <1000000>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&dspi1 { 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun dflash1: flash@0 { 54*4882a593Smuzhiyun #address-cells = <1>; 55*4882a593Smuzhiyun #size-cells = <1>; 56*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 57*4882a593Smuzhiyun reg = <0>; 58*4882a593Smuzhiyun spi-max-frequency = <1000000>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&dspi2 { 63*4882a593Smuzhiyun status = "okay"; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun dflash2: flash@0 { 66*4882a593Smuzhiyun #address-cells = <1>; 67*4882a593Smuzhiyun #size-cells = <1>; 68*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 69*4882a593Smuzhiyun reg = <0>; 70*4882a593Smuzhiyun spi-max-frequency = <1000000>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&esdhc0 { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&esdhc1 { 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&fspi { 83*4882a593Smuzhiyun status = "okay"; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun mt35xu512aba0: flash@0 { 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <1>; 88*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 89*4882a593Smuzhiyun m25p,fast-read; 90*4882a593Smuzhiyun spi-max-frequency = <50000000>; 91*4882a593Smuzhiyun reg = <0>; 92*4882a593Smuzhiyun spi-rx-bus-width = <8>; 93*4882a593Smuzhiyun spi-tx-bus-width = <8>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun&i2c0 { 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun i2c-mux@77 { 101*4882a593Smuzhiyun compatible = "nxp,pca9547"; 102*4882a593Smuzhiyun reg = <0x77>; 103*4882a593Smuzhiyun #address-cells = <1>; 104*4882a593Smuzhiyun #size-cells = <0>; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun i2c@2 { 107*4882a593Smuzhiyun #address-cells = <1>; 108*4882a593Smuzhiyun #size-cells = <0>; 109*4882a593Smuzhiyun reg = <0x2>; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun power-monitor@40 { 112*4882a593Smuzhiyun compatible = "ti,ina220"; 113*4882a593Smuzhiyun reg = <0x40>; 114*4882a593Smuzhiyun shunt-resistor = <500>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun power-monitor@41 { 118*4882a593Smuzhiyun compatible = "ti,ina220"; 119*4882a593Smuzhiyun reg = <0x41>; 120*4882a593Smuzhiyun shunt-resistor = <1000>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun i2c@3 { 125*4882a593Smuzhiyun #address-cells = <1>; 126*4882a593Smuzhiyun #size-cells = <0>; 127*4882a593Smuzhiyun reg = <0x3>; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun temperature-sensor@4c { 130*4882a593Smuzhiyun compatible = "nxp,sa56004"; 131*4882a593Smuzhiyun reg = <0x4c>; 132*4882a593Smuzhiyun vcc-supply = <&sb_3v3>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun temperature-sensor@4d { 136*4882a593Smuzhiyun compatible = "nxp,sa56004"; 137*4882a593Smuzhiyun reg = <0x4d>; 138*4882a593Smuzhiyun vcc-supply = <&sb_3v3>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun rtc@51 { 142*4882a593Smuzhiyun compatible = "nxp,pcf2129"; 143*4882a593Smuzhiyun reg = <0x51>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun&sata0 { 150*4882a593Smuzhiyun status = "okay"; 151*4882a593Smuzhiyun}; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun&sata1 { 154*4882a593Smuzhiyun status = "okay"; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&sata2 { 158*4882a593Smuzhiyun status = "okay"; 159*4882a593Smuzhiyun}; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun&sata3 { 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun}; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun&uart0 { 166*4882a593Smuzhiyun status = "okay"; 167*4882a593Smuzhiyun}; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun&uart1 { 170*4882a593Smuzhiyun status = "okay"; 171*4882a593Smuzhiyun}; 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun&usb0 { 174*4882a593Smuzhiyun status = "okay"; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun&usb1 { 178*4882a593Smuzhiyun status = "okay"; 179*4882a593Smuzhiyun}; 180