1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Samsung Exynos5433 TM2E board device tree source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on 8*4882a593Smuzhiyun * Samsung Exynos5433 SoC. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "exynos5433-tm2-common.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Samsung TM2E board"; 15*4882a593Smuzhiyun compatible = "samsung,tm2e", "samsung,exynos5433"; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&cmu_disp { 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned 21*4882a593Smuzhiyun * clocks properties for DISP CMU for each board to keep them together 22*4882a593Smuzhiyun * for easier review and maintenance. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, 25*4882a593Smuzhiyun <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, 26*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, 27*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, 28*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DSIM0>, 29*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, 30*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, 31*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, 32*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, 33*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_DISP_PLL>, 34*4882a593Smuzhiyun <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, 35*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, 36*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; 37*4882a593Smuzhiyun assigned-clock-parents = <0>, <0>, 38*4882a593Smuzhiyun <&cmu_mif CLK_ACLK_DISP_333>, 39*4882a593Smuzhiyun <&cmu_mif CLK_SCLK_DSIM0_DISP>, 40*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, 41*4882a593Smuzhiyun <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 42*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, 43*4882a593Smuzhiyun <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, 44*4882a593Smuzhiyun <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, 45*4882a593Smuzhiyun <&cmu_disp CLK_FOUT_DISP_PLL>, 46*4882a593Smuzhiyun <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, 47*4882a593Smuzhiyun <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, 48*4882a593Smuzhiyun <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; 49*4882a593Smuzhiyun assigned-clock-rates = <278000000>, <400000000>; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&dsi { 53*4882a593Smuzhiyun panel@0 { 54*4882a593Smuzhiyun compatible = "samsung,s6e3hf2"; 55*4882a593Smuzhiyun reg = <0>; 56*4882a593Smuzhiyun vdd3-supply = <&ldo27_reg>; 57*4882a593Smuzhiyun vci-supply = <&ldo28_reg>; 58*4882a593Smuzhiyun reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>; 59*4882a593Smuzhiyun enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&ldo31_reg { 64*4882a593Smuzhiyun regulator-name = "TSP_VDD_1.8V_AP"; 65*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 66*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun&ldo38_reg { 70*4882a593Smuzhiyun regulator-name = "VCC_3.3V_MOTOR_AP"; 71*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 72*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&stmfts { 76*4882a593Smuzhiyun touchscreen-size-x = <1599>; 77*4882a593Smuzhiyun touchscreen-size-y = <2559>; 78*4882a593Smuzhiyun touch-key-connected; 79*4882a593Smuzhiyun ledvdd-supply = <&ldo33_reg>; 80*4882a593Smuzhiyun}; 81