xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Samsung Exynos5433 TM2 board device tree source
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Common device tree source file for Samsung's TM2 and TM2E boards
8*4882a593Smuzhiyun * which are based on Samsung Exynos5433 SoC.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/dts-v1/;
12*4882a593Smuzhiyun#include "exynos5433.dtsi"
13*4882a593Smuzhiyun#include <dt-bindings/clock/samsung,s2mps11.h>
14*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
15*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
16*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
17*4882a593Smuzhiyun#include <dt-bindings/sound/samsung-i2s.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun/ {
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		gsc0 = &gsc_0;
22*4882a593Smuzhiyun		gsc1 = &gsc_1;
23*4882a593Smuzhiyun		gsc2 = &gsc_2;
24*4882a593Smuzhiyun		pinctrl0 = &pinctrl_alive;
25*4882a593Smuzhiyun		pinctrl1 = &pinctrl_aud;
26*4882a593Smuzhiyun		pinctrl2 = &pinctrl_cpif;
27*4882a593Smuzhiyun		pinctrl3 = &pinctrl_ese;
28*4882a593Smuzhiyun		pinctrl4 = &pinctrl_finger;
29*4882a593Smuzhiyun		pinctrl5 = &pinctrl_fsys;
30*4882a593Smuzhiyun		pinctrl6 = &pinctrl_imem;
31*4882a593Smuzhiyun		pinctrl7 = &pinctrl_nfc;
32*4882a593Smuzhiyun		pinctrl8 = &pinctrl_peric;
33*4882a593Smuzhiyun		pinctrl9 = &pinctrl_touch;
34*4882a593Smuzhiyun		serial0 = &serial_0;
35*4882a593Smuzhiyun		serial1 = &serial_1;
36*4882a593Smuzhiyun		serial2 = &serial_2;
37*4882a593Smuzhiyun		serial3 = &serial_3;
38*4882a593Smuzhiyun		spi0 = &spi_0;
39*4882a593Smuzhiyun		spi1 = &spi_1;
40*4882a593Smuzhiyun		spi2 = &spi_2;
41*4882a593Smuzhiyun		spi3 = &spi_3;
42*4882a593Smuzhiyun		spi4 = &spi_4;
43*4882a593Smuzhiyun		mshc0 = &mshc_0;
44*4882a593Smuzhiyun		mshc2 = &mshc_2;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	chosen {
48*4882a593Smuzhiyun		stdout-path = &serial_1;
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	memory@20000000 {
52*4882a593Smuzhiyun		device_type = "memory";
53*4882a593Smuzhiyun		reg = <0x0 0x20000000 0x0 0xc0000000>;
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	gpio-keys {
57*4882a593Smuzhiyun		compatible = "gpio-keys";
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun		power-key {
60*4882a593Smuzhiyun			gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
62*4882a593Smuzhiyun			label = "power key";
63*4882a593Smuzhiyun			debounce-interval = <10>;
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		volume-up-key {
67*4882a593Smuzhiyun			gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
69*4882a593Smuzhiyun			label = "volume-up key";
70*4882a593Smuzhiyun			debounce-interval = <10>;
71*4882a593Smuzhiyun		};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun		volume-down-key {
74*4882a593Smuzhiyun			gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
76*4882a593Smuzhiyun			label = "volume-down key";
77*4882a593Smuzhiyun			debounce-interval = <10>;
78*4882a593Smuzhiyun		};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun		homepage-key {
81*4882a593Smuzhiyun			gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
83*4882a593Smuzhiyun			label = "homepage key";
84*4882a593Smuzhiyun			debounce-interval = <10>;
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun	};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	i2c_max98504: i2c-gpio-0 {
89*4882a593Smuzhiyun		compatible = "i2c-gpio";
90*4882a593Smuzhiyun		sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>;
91*4882a593Smuzhiyun		scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>;
92*4882a593Smuzhiyun		i2c-gpio,delay-us = <2>;
93*4882a593Smuzhiyun		#address-cells = <1>;
94*4882a593Smuzhiyun		#size-cells = <0>;
95*4882a593Smuzhiyun		status = "okay";
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		max98504: max98504@31 {
98*4882a593Smuzhiyun			compatible = "maxim,max98504";
99*4882a593Smuzhiyun			reg = <0x31>;
100*4882a593Smuzhiyun			maxim,rx-path = <1>;
101*4882a593Smuzhiyun			maxim,tx-path = <1>;
102*4882a593Smuzhiyun			maxim,tx-channel-mask = <3>;
103*4882a593Smuzhiyun			maxim,tx-channel-source = <2>;
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun	};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	irda_regulator: irda-regulator {
108*4882a593Smuzhiyun		compatible = "regulator-fixed";
109*4882a593Smuzhiyun		enable-active-high;
110*4882a593Smuzhiyun		gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
111*4882a593Smuzhiyun		regulator-name = "irda_regulator";
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	sound {
115*4882a593Smuzhiyun		compatible = "samsung,tm2-audio";
116*4882a593Smuzhiyun		audio-codec = <&wm5110>, <&hdmi>;
117*4882a593Smuzhiyun		i2s-controller = <&i2s0 0>, <&i2s1 0>;
118*4882a593Smuzhiyun		audio-amplifier = <&max98504>;
119*4882a593Smuzhiyun		mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
120*4882a593Smuzhiyun		model = "wm5110";
121*4882a593Smuzhiyun		samsung,audio-routing =
122*4882a593Smuzhiyun			/* Headphone */
123*4882a593Smuzhiyun			"HP", "HPOUT1L",
124*4882a593Smuzhiyun			"HP", "HPOUT1R",
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun			/* Speaker */
127*4882a593Smuzhiyun			"SPK", "SPKOUT",
128*4882a593Smuzhiyun			"SPKOUT", "HPOUT2L",
129*4882a593Smuzhiyun			"SPKOUT", "HPOUT2R",
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun			/* Receiver */
132*4882a593Smuzhiyun			"RCV", "HPOUT3L",
133*4882a593Smuzhiyun			"RCV", "HPOUT3R";
134*4882a593Smuzhiyun		status = "okay";
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&adc {
139*4882a593Smuzhiyun	vdd-supply = <&ldo3_reg>;
140*4882a593Smuzhiyun	status = "okay";
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	thermistor-ap {
143*4882a593Smuzhiyun		compatible = "murata,ncp03wf104";
144*4882a593Smuzhiyun		pullup-uv = <1800000>;
145*4882a593Smuzhiyun		pullup-ohm = <100000>;
146*4882a593Smuzhiyun		pulldown-ohm = <0>;
147*4882a593Smuzhiyun		io-channels = <&adc 0>;
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	thermistor-battery {
151*4882a593Smuzhiyun		compatible = "murata,ncp03wf104";
152*4882a593Smuzhiyun		pullup-uv = <1800000>;
153*4882a593Smuzhiyun		pullup-ohm = <100000>;
154*4882a593Smuzhiyun		pulldown-ohm = <0>;
155*4882a593Smuzhiyun		io-channels = <&adc 1>;
156*4882a593Smuzhiyun		#thermal-sensor-cells = <0>;
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun	thermistor-charger {
160*4882a593Smuzhiyun		compatible = "murata,ncp03wf104";
161*4882a593Smuzhiyun		pullup-uv = <1800000>;
162*4882a593Smuzhiyun		pullup-ohm = <100000>;
163*4882a593Smuzhiyun		pulldown-ohm = <0>;
164*4882a593Smuzhiyun		io-channels = <&adc 2>;
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun&bus_g2d_400 {
169*4882a593Smuzhiyun	devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
170*4882a593Smuzhiyun	vdd-supply = <&buck4_reg>;
171*4882a593Smuzhiyun	exynos,saturation-ratio = <10>;
172*4882a593Smuzhiyun	status = "okay";
173*4882a593Smuzhiyun};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun&bus_g2d_266 {
176*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
177*4882a593Smuzhiyun	status = "okay";
178*4882a593Smuzhiyun};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun&bus_gscl {
181*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
182*4882a593Smuzhiyun	status = "okay";
183*4882a593Smuzhiyun};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun&bus_hevc {
186*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
187*4882a593Smuzhiyun	status = "okay";
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&bus_jpeg {
191*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
192*4882a593Smuzhiyun	status = "okay";
193*4882a593Smuzhiyun};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun&bus_mfc {
196*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&bus_mscl {
201*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
202*4882a593Smuzhiyun	status = "okay";
203*4882a593Smuzhiyun};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun&bus_noc0 {
206*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
207*4882a593Smuzhiyun	status = "okay";
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&bus_noc1 {
211*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
212*4882a593Smuzhiyun	status = "okay";
213*4882a593Smuzhiyun};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun&bus_noc2 {
216*4882a593Smuzhiyun	devfreq = <&bus_g2d_400>;
217*4882a593Smuzhiyun	status = "okay";
218*4882a593Smuzhiyun};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun&cmu_aud {
221*4882a593Smuzhiyun	assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
222*4882a593Smuzhiyun		<&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
223*4882a593Smuzhiyun		<&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
224*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_AUD_PLL>,
225*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
226*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_SCLK_AUDIO0>,
227*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_SCLK_AUDIO1>,
228*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_SCLK_SPDIF>,
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun		<&cmu_aud CLK_DIV_AUD_CA5>,
231*4882a593Smuzhiyun		<&cmu_aud CLK_DIV_ACLK_AUD>,
232*4882a593Smuzhiyun		<&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
233*4882a593Smuzhiyun		<&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
234*4882a593Smuzhiyun		<&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
235*4882a593Smuzhiyun		<&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
236*4882a593Smuzhiyun		<&cmu_aud CLK_DIV_SCLK_AUD_UART>,
237*4882a593Smuzhiyun		<&cmu_top CLK_DIV_SCLK_AUDIO0>,
238*4882a593Smuzhiyun		<&cmu_top CLK_DIV_SCLK_AUDIO1>,
239*4882a593Smuzhiyun		<&cmu_top CLK_DIV_SCLK_PCM1>,
240*4882a593Smuzhiyun		<&cmu_top CLK_DIV_SCLK_I2S1>;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun	assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
243*4882a593Smuzhiyun		<&cmu_aud CLK_MOUT_AUD_PLL_USER>,
244*4882a593Smuzhiyun		<&cmu_aud CLK_MOUT_AUD_PLL_USER>,
245*4882a593Smuzhiyun		<&cmu_top CLK_FOUT_AUD_PLL>,
246*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_AUD_PLL>,
247*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
248*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
249*4882a593Smuzhiyun		<&cmu_top CLK_SCLK_AUDIO0>;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun	assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
252*4882a593Smuzhiyun		<196608001>, <65536001>, <32768001>, <49152001>,
253*4882a593Smuzhiyun		<2048001>, <24576001>, <196608001>,
254*4882a593Smuzhiyun		<24576001>, <98304001>, <2048001>, <49152001>;
255*4882a593Smuzhiyun};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun&cmu_fsys {
258*4882a593Smuzhiyun	assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
259*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
260*4882a593Smuzhiyun		<&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
261*4882a593Smuzhiyun		<&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
262*4882a593Smuzhiyun		<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
263*4882a593Smuzhiyun		<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
264*4882a593Smuzhiyun		<&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
265*4882a593Smuzhiyun		<&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
266*4882a593Smuzhiyun		<&cmu_top CLK_DIV_SCLK_USBDRD30>,
267*4882a593Smuzhiyun		<&cmu_top CLK_DIV_SCLK_USBHOST30>;
268*4882a593Smuzhiyun	assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
269*4882a593Smuzhiyun		<&cmu_top CLK_MOUT_BUS_PLL_USER>,
270*4882a593Smuzhiyun		<&cmu_top CLK_SCLK_USBDRD30_FSYS>,
271*4882a593Smuzhiyun		<&cmu_top CLK_SCLK_USBHOST30_FSYS>,
272*4882a593Smuzhiyun		<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
273*4882a593Smuzhiyun		<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
274*4882a593Smuzhiyun		<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
275*4882a593Smuzhiyun		<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
276*4882a593Smuzhiyun	assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
277*4882a593Smuzhiyun			       <66700000>, <66700000>;
278*4882a593Smuzhiyun};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun&cmu_gscl {
281*4882a593Smuzhiyun	assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
282*4882a593Smuzhiyun			  <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
283*4882a593Smuzhiyun	assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
284*4882a593Smuzhiyun				 <&cmu_top CLK_ACLK_GSCL_333>;
285*4882a593Smuzhiyun};
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun&cmu_mfc {
288*4882a593Smuzhiyun	assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
289*4882a593Smuzhiyun	assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
290*4882a593Smuzhiyun};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun&cmu_mif {
293*4882a593Smuzhiyun	assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
294*4882a593Smuzhiyun	assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
295*4882a593Smuzhiyun	assigned-clock-rates = <0>, <333000000>;
296*4882a593Smuzhiyun};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun&cmu_mscl {
299*4882a593Smuzhiyun	assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
300*4882a593Smuzhiyun			  <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
301*4882a593Smuzhiyun			  <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
302*4882a593Smuzhiyun			  <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
303*4882a593Smuzhiyun	assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
304*4882a593Smuzhiyun				 <&cmu_top CLK_SCLK_JPEG_MSCL>,
305*4882a593Smuzhiyun				 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
306*4882a593Smuzhiyun				 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
307*4882a593Smuzhiyun};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun&cmu_top {
310*4882a593Smuzhiyun	assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
311*4882a593Smuzhiyun	assigned-clock-rates = <196608001>;
312*4882a593Smuzhiyun};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun&cpu0 {
315*4882a593Smuzhiyun	cpu-supply = <&buck3_reg>;
316*4882a593Smuzhiyun};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun&cpu4 {
319*4882a593Smuzhiyun	cpu-supply = <&buck2_reg>;
320*4882a593Smuzhiyun};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun&decon {
323*4882a593Smuzhiyun	status = "okay";
324*4882a593Smuzhiyun};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun&decon_tv {
327*4882a593Smuzhiyun	status = "okay";
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun	ports {
330*4882a593Smuzhiyun		#address-cells = <1>;
331*4882a593Smuzhiyun		#size-cells = <0>;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun		port@0 {
334*4882a593Smuzhiyun			reg = <0>;
335*4882a593Smuzhiyun			tv_to_hdmi: endpoint {
336*4882a593Smuzhiyun				remote-endpoint = <&hdmi_to_tv>;
337*4882a593Smuzhiyun			};
338*4882a593Smuzhiyun		};
339*4882a593Smuzhiyun	};
340*4882a593Smuzhiyun};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun&dsi {
343*4882a593Smuzhiyun	status = "okay";
344*4882a593Smuzhiyun	vddcore-supply = <&ldo6_reg>;
345*4882a593Smuzhiyun	vddio-supply = <&ldo7_reg>;
346*4882a593Smuzhiyun	samsung,burst-clock-frequency = <512000000>;
347*4882a593Smuzhiyun	samsung,esc-clock-frequency = <16000000>;
348*4882a593Smuzhiyun	samsung,pll-clock-frequency = <24000000>;
349*4882a593Smuzhiyun	pinctrl-names = "default";
350*4882a593Smuzhiyun	pinctrl-0 = <&te_irq>;
351*4882a593Smuzhiyun};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun&gpu {
354*4882a593Smuzhiyun	mali-supply = <&buck6_reg>;
355*4882a593Smuzhiyun	status = "okay";
356*4882a593Smuzhiyun};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun&hdmi {
359*4882a593Smuzhiyun	hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
360*4882a593Smuzhiyun	status = "okay";
361*4882a593Smuzhiyun	vdd-supply = <&ldo6_reg>;
362*4882a593Smuzhiyun	vdd_osc-supply = <&ldo7_reg>;
363*4882a593Smuzhiyun	vdd_pll-supply = <&ldo6_reg>;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun	ports {
366*4882a593Smuzhiyun		#address-cells = <1>;
367*4882a593Smuzhiyun		#size-cells = <0>;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun		port@0 {
370*4882a593Smuzhiyun			reg = <0>;
371*4882a593Smuzhiyun			hdmi_to_tv: endpoint {
372*4882a593Smuzhiyun				remote-endpoint = <&tv_to_hdmi>;
373*4882a593Smuzhiyun			};
374*4882a593Smuzhiyun		};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun		port@1 {
377*4882a593Smuzhiyun			reg = <1>;
378*4882a593Smuzhiyun			hdmi_to_mhl: endpoint {
379*4882a593Smuzhiyun				remote-endpoint = <&mhl_to_hdmi>;
380*4882a593Smuzhiyun			};
381*4882a593Smuzhiyun		};
382*4882a593Smuzhiyun	};
383*4882a593Smuzhiyun};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun&hsi2c_0 {
386*4882a593Smuzhiyun	status = "okay";
387*4882a593Smuzhiyun	clock-frequency = <2500000>;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun	s2mps13-pmic@66 {
390*4882a593Smuzhiyun		compatible = "samsung,s2mps13-pmic";
391*4882a593Smuzhiyun		interrupt-parent = <&gpa0>;
392*4882a593Smuzhiyun		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
393*4882a593Smuzhiyun		reg = <0x66>;
394*4882a593Smuzhiyun		samsung,s2mps11-wrstbi-ground;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun		s2mps13_osc: clocks {
397*4882a593Smuzhiyun			compatible = "samsung,s2mps13-clk";
398*4882a593Smuzhiyun			#clock-cells = <1>;
399*4882a593Smuzhiyun			clock-output-names = "s2mps13_ap", "s2mps13_cp",
400*4882a593Smuzhiyun				"s2mps13_bt";
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun		regulators {
404*4882a593Smuzhiyun			ldo1_reg: LDO1 {
405*4882a593Smuzhiyun				regulator-name = "VDD_ALIVE_0.9V_AP";
406*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
407*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
408*4882a593Smuzhiyun				regulator-always-on;
409*4882a593Smuzhiyun			};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun			ldo2_reg: LDO2 {
412*4882a593Smuzhiyun				regulator-name = "VDDQ_MMC2_2.8V_AP";
413*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
414*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
415*4882a593Smuzhiyun				regulator-always-on;
416*4882a593Smuzhiyun				regulator-state-mem {
417*4882a593Smuzhiyun					regulator-off-in-suspend;
418*4882a593Smuzhiyun				};
419*4882a593Smuzhiyun			};
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun			ldo3_reg: LDO3 {
422*4882a593Smuzhiyun				regulator-name = "VDD1_E_1.8V_AP";
423*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
424*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
425*4882a593Smuzhiyun				regulator-always-on;
426*4882a593Smuzhiyun			};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun			ldo4_reg: LDO4 {
429*4882a593Smuzhiyun				regulator-name = "VDD10_MIF_PLL_1.0V_AP";
430*4882a593Smuzhiyun				regulator-min-microvolt = <1300000>;
431*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
432*4882a593Smuzhiyun				regulator-always-on;
433*4882a593Smuzhiyun				regulator-state-mem {
434*4882a593Smuzhiyun					regulator-off-in-suspend;
435*4882a593Smuzhiyun				};
436*4882a593Smuzhiyun			};
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun			ldo5_reg: LDO5 {
439*4882a593Smuzhiyun				regulator-name = "VDD10_DPLL_1.0V_AP";
440*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
441*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
442*4882a593Smuzhiyun				regulator-always-on;
443*4882a593Smuzhiyun				regulator-state-mem {
444*4882a593Smuzhiyun					regulator-off-in-suspend;
445*4882a593Smuzhiyun				};
446*4882a593Smuzhiyun			};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun			ldo6_reg: LDO6 {
449*4882a593Smuzhiyun				regulator-name = "VDD10_MIPI2L_1.0V_AP";
450*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
451*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
452*4882a593Smuzhiyun				regulator-state-mem {
453*4882a593Smuzhiyun					regulator-off-in-suspend;
454*4882a593Smuzhiyun				};
455*4882a593Smuzhiyun			};
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun			ldo7_reg: LDO7 {
458*4882a593Smuzhiyun				regulator-name = "VDD18_MIPI2L_1.8V_AP";
459*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
460*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
461*4882a593Smuzhiyun				regulator-always-on;
462*4882a593Smuzhiyun				regulator-state-mem {
463*4882a593Smuzhiyun					regulator-off-in-suspend;
464*4882a593Smuzhiyun				};
465*4882a593Smuzhiyun			};
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun			ldo8_reg: LDO8 {
468*4882a593Smuzhiyun				regulator-name = "VDD18_LLI_1.8V_AP";
469*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
470*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
471*4882a593Smuzhiyun				regulator-always-on;
472*4882a593Smuzhiyun				regulator-state-mem {
473*4882a593Smuzhiyun					regulator-off-in-suspend;
474*4882a593Smuzhiyun				};
475*4882a593Smuzhiyun			};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun			ldo9_reg: LDO9 {
478*4882a593Smuzhiyun				regulator-name = "VDD18_ABB_ETC_1.8V_AP";
479*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
480*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
481*4882a593Smuzhiyun				regulator-always-on;
482*4882a593Smuzhiyun				regulator-state-mem {
483*4882a593Smuzhiyun					regulator-off-in-suspend;
484*4882a593Smuzhiyun				};
485*4882a593Smuzhiyun			};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun			ldo10_reg: LDO10 {
488*4882a593Smuzhiyun				regulator-name = "VDD33_USB30_3.0V_AP";
489*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
490*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
491*4882a593Smuzhiyun				regulator-state-mem {
492*4882a593Smuzhiyun					regulator-off-in-suspend;
493*4882a593Smuzhiyun				};
494*4882a593Smuzhiyun			};
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun			ldo11_reg: LDO11 {
497*4882a593Smuzhiyun				regulator-name = "VDD_INT_M_1.0V_AP";
498*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
499*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
500*4882a593Smuzhiyun				regulator-always-on;
501*4882a593Smuzhiyun				regulator-state-mem {
502*4882a593Smuzhiyun					regulator-off-in-suspend;
503*4882a593Smuzhiyun				};
504*4882a593Smuzhiyun			};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun			ldo12_reg: LDO12 {
507*4882a593Smuzhiyun				regulator-name = "VDD_KFC_M_1.1V_AP";
508*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
509*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
510*4882a593Smuzhiyun				regulator-always-on;
511*4882a593Smuzhiyun			};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun			ldo13_reg: LDO13 {
514*4882a593Smuzhiyun				regulator-name = "VDD_G3D_M_0.95V_AP";
515*4882a593Smuzhiyun				regulator-min-microvolt = <950000>;
516*4882a593Smuzhiyun				regulator-max-microvolt = <950000>;
517*4882a593Smuzhiyun				regulator-always-on;
518*4882a593Smuzhiyun				regulator-state-mem {
519*4882a593Smuzhiyun					regulator-off-in-suspend;
520*4882a593Smuzhiyun				};
521*4882a593Smuzhiyun			};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun			ldo14_reg: LDO14 {
524*4882a593Smuzhiyun				regulator-name = "VDDQ_M1_LDO_1.2V_AP";
525*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
526*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
527*4882a593Smuzhiyun				regulator-always-on;
528*4882a593Smuzhiyun				regulator-state-mem {
529*4882a593Smuzhiyun					regulator-off-in-suspend;
530*4882a593Smuzhiyun				};
531*4882a593Smuzhiyun			};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun			ldo15_reg: LDO15 {
534*4882a593Smuzhiyun				regulator-name = "VDDQ_M2_LDO_1.2V_AP";
535*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
536*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
537*4882a593Smuzhiyun				regulator-always-on;
538*4882a593Smuzhiyun				regulator-state-mem {
539*4882a593Smuzhiyun					regulator-off-in-suspend;
540*4882a593Smuzhiyun				};
541*4882a593Smuzhiyun			};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun			ldo16_reg: LDO16 {
544*4882a593Smuzhiyun				regulator-name = "VDDQ_EFUSE";
545*4882a593Smuzhiyun				regulator-min-microvolt = <1400000>;
546*4882a593Smuzhiyun				regulator-max-microvolt = <3400000>;
547*4882a593Smuzhiyun				regulator-always-on;
548*4882a593Smuzhiyun			};
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun			ldo17_reg: LDO17 {
551*4882a593Smuzhiyun				regulator-name = "V_TFLASH_2.8V_AP";
552*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
553*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
554*4882a593Smuzhiyun			};
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun			ldo18_reg: LDO18 {
557*4882a593Smuzhiyun				regulator-name = "V_CODEC_1.8V_AP";
558*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
559*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
560*4882a593Smuzhiyun			};
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun			ldo19_reg: LDO19 {
563*4882a593Smuzhiyun				regulator-name = "VDDA_1.8V_COMP";
564*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
565*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
566*4882a593Smuzhiyun				regulator-always-on;
567*4882a593Smuzhiyun			};
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun			ldo20_reg: LDO20 {
570*4882a593Smuzhiyun				regulator-name = "VCC_2.8V_AP";
571*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
572*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
573*4882a593Smuzhiyun				regulator-always-on;
574*4882a593Smuzhiyun			};
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun			ldo21_reg: LDO21 {
577*4882a593Smuzhiyun				regulator-name = "VT_CAM_1.8V";
578*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
579*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
580*4882a593Smuzhiyun			};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun			ldo22_reg: LDO22 {
583*4882a593Smuzhiyun				regulator-name = "CAM_IO_1.8V_AP";
584*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
585*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
586*4882a593Smuzhiyun			};
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun			ldo23_reg: LDO23 {
589*4882a593Smuzhiyun				regulator-name = "CAM_SEN_CORE_1.05V_AP";
590*4882a593Smuzhiyun				regulator-min-microvolt = <1050000>;
591*4882a593Smuzhiyun				regulator-max-microvolt = <1050000>;
592*4882a593Smuzhiyun			};
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun			ldo24_reg: LDO24 {
595*4882a593Smuzhiyun				regulator-name = "VT_CAM_1.2V";
596*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
597*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
598*4882a593Smuzhiyun			};
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun			ldo25_reg: LDO25 {
601*4882a593Smuzhiyun				regulator-name = "UNUSED_LDO25";
602*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
603*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
604*4882a593Smuzhiyun			};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun			ldo26_reg: LDO26 {
607*4882a593Smuzhiyun				regulator-name = "CAM_AF_2.8V_AP";
608*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
609*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
610*4882a593Smuzhiyun			};
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun			ldo27_reg: LDO27 {
613*4882a593Smuzhiyun				regulator-name = "VCC_3.0V_LCD_AP";
614*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
615*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
616*4882a593Smuzhiyun			};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun			ldo28_reg: LDO28 {
619*4882a593Smuzhiyun				regulator-name = "VCC_1.8V_LCD_AP";
620*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
621*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
622*4882a593Smuzhiyun			};
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun			ldo29_reg: LDO29 {
625*4882a593Smuzhiyun				regulator-name = "VT_CAM_2.8V";
626*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
627*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
628*4882a593Smuzhiyun			};
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun			ldo30_reg: LDO30 {
631*4882a593Smuzhiyun				regulator-name = "TSP_AVDD_3.3V_AP";
632*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
633*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
634*4882a593Smuzhiyun			};
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun			ldo31_reg: LDO31 {
637*4882a593Smuzhiyun				/*
638*4882a593Smuzhiyun				 * LDO31 differs from target to target,
639*4882a593Smuzhiyun				 * its definition is in the .dts
640*4882a593Smuzhiyun				 */
641*4882a593Smuzhiyun			};
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun			ldo32_reg: LDO32 {
644*4882a593Smuzhiyun				regulator-name = "VTOUCH_1.8V_AP";
645*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
646*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
647*4882a593Smuzhiyun			};
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun			ldo33_reg: LDO33 {
650*4882a593Smuzhiyun				regulator-name = "VTOUCH_LED_3.3V";
651*4882a593Smuzhiyun				regulator-min-microvolt = <2500000>;
652*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
653*4882a593Smuzhiyun				regulator-ramp-delay = <12500>;
654*4882a593Smuzhiyun			};
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun			ldo34_reg: LDO34 {
657*4882a593Smuzhiyun				regulator-name = "VCC_1.8V_MHL_AP";
658*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
659*4882a593Smuzhiyun				regulator-max-microvolt = <2100000>;
660*4882a593Smuzhiyun			};
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun			ldo35_reg: LDO35 {
663*4882a593Smuzhiyun				regulator-name = "OIS_VM_2.8V";
664*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
665*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
666*4882a593Smuzhiyun			};
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun			ldo36_reg: LDO36 {
669*4882a593Smuzhiyun				regulator-name = "VSIL_1.0V";
670*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
671*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
672*4882a593Smuzhiyun			};
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun			ldo37_reg: LDO37 {
675*4882a593Smuzhiyun				regulator-name = "VF_1.8V";
676*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
677*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
678*4882a593Smuzhiyun			};
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun			ldo38_reg: LDO38 {
681*4882a593Smuzhiyun				/*
682*4882a593Smuzhiyun				 * LDO38 differs from target to target,
683*4882a593Smuzhiyun				 * its definition is in the .dts
684*4882a593Smuzhiyun				 */
685*4882a593Smuzhiyun			};
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun			ldo39_reg: LDO39 {
688*4882a593Smuzhiyun				regulator-name = "V_HRM_1.8V";
689*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
690*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
691*4882a593Smuzhiyun			};
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun			ldo40_reg: LDO40 {
694*4882a593Smuzhiyun				regulator-name = "V_HRM_3.3V";
695*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
696*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
697*4882a593Smuzhiyun			};
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun			buck1_reg: BUCK1 {
700*4882a593Smuzhiyun				regulator-name = "VDD_MIF_0.9V_AP";
701*4882a593Smuzhiyun				regulator-min-microvolt = <600000>;
702*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
703*4882a593Smuzhiyun				regulator-always-on;
704*4882a593Smuzhiyun				regulator-state-mem {
705*4882a593Smuzhiyun					regulator-off-in-suspend;
706*4882a593Smuzhiyun				};
707*4882a593Smuzhiyun			};
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun			buck2_reg: BUCK2 {
710*4882a593Smuzhiyun				regulator-name = "VDD_EGL_1.0V_AP";
711*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
712*4882a593Smuzhiyun				regulator-max-microvolt = <1300000>;
713*4882a593Smuzhiyun				regulator-always-on;
714*4882a593Smuzhiyun				regulator-state-mem {
715*4882a593Smuzhiyun					regulator-off-in-suspend;
716*4882a593Smuzhiyun				};
717*4882a593Smuzhiyun			};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun			buck3_reg: BUCK3 {
720*4882a593Smuzhiyun				regulator-name = "VDD_KFC_1.0V_AP";
721*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
722*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
723*4882a593Smuzhiyun				regulator-always-on;
724*4882a593Smuzhiyun				regulator-state-mem {
725*4882a593Smuzhiyun					regulator-off-in-suspend;
726*4882a593Smuzhiyun				};
727*4882a593Smuzhiyun			};
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun			buck4_reg: BUCK4 {
730*4882a593Smuzhiyun				regulator-name = "VDD_INT_0.95V_AP";
731*4882a593Smuzhiyun				regulator-min-microvolt = <600000>;
732*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
733*4882a593Smuzhiyun				regulator-always-on;
734*4882a593Smuzhiyun				regulator-state-mem {
735*4882a593Smuzhiyun					regulator-off-in-suspend;
736*4882a593Smuzhiyun				};
737*4882a593Smuzhiyun			};
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun			buck5_reg: BUCK5 {
740*4882a593Smuzhiyun				regulator-name = "VDD_DISP_CAM0_0.9V_AP";
741*4882a593Smuzhiyun				regulator-min-microvolt = <600000>;
742*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
743*4882a593Smuzhiyun				regulator-always-on;
744*4882a593Smuzhiyun				regulator-state-mem {
745*4882a593Smuzhiyun					regulator-off-in-suspend;
746*4882a593Smuzhiyun				};
747*4882a593Smuzhiyun			};
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun			buck6_reg: BUCK6 {
750*4882a593Smuzhiyun				regulator-name = "VDD_G3D_0.9V_AP";
751*4882a593Smuzhiyun				regulator-min-microvolt = <600000>;
752*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
753*4882a593Smuzhiyun				regulator-always-on;
754*4882a593Smuzhiyun				regulator-state-mem {
755*4882a593Smuzhiyun					regulator-off-in-suspend;
756*4882a593Smuzhiyun				};
757*4882a593Smuzhiyun			};
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun			buck7_reg: BUCK7 {
760*4882a593Smuzhiyun				regulator-name = "VDD_MEM1_1.2V_AP";
761*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
762*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
763*4882a593Smuzhiyun				regulator-always-on;
764*4882a593Smuzhiyun			};
765*4882a593Smuzhiyun
766*4882a593Smuzhiyun			buck8_reg: BUCK8 {
767*4882a593Smuzhiyun				regulator-name = "VDD_LLDO_1.35V_AP";
768*4882a593Smuzhiyun				regulator-min-microvolt = <1350000>;
769*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
770*4882a593Smuzhiyun				regulator-always-on;
771*4882a593Smuzhiyun			};
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun			buck9_reg: BUCK9 {
774*4882a593Smuzhiyun				regulator-name = "VDD_MLDO_2.0V_AP";
775*4882a593Smuzhiyun				regulator-min-microvolt = <1350000>;
776*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
777*4882a593Smuzhiyun				regulator-always-on;
778*4882a593Smuzhiyun			};
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun			buck10_reg: BUCK10 {
781*4882a593Smuzhiyun				regulator-name = "vdd_mem2";
782*4882a593Smuzhiyun				regulator-min-microvolt = <550000>;
783*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
784*4882a593Smuzhiyun				regulator-always-on;
785*4882a593Smuzhiyun			};
786*4882a593Smuzhiyun		};
787*4882a593Smuzhiyun	};
788*4882a593Smuzhiyun};
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun&hsi2c_4 {
791*4882a593Smuzhiyun	status = "okay";
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun	s3fwrn5: nfc@27 {
794*4882a593Smuzhiyun		compatible = "samsung,s3fwrn5-i2c";
795*4882a593Smuzhiyun		reg = <0x27>;
796*4882a593Smuzhiyun		interrupt-parent = <&gpa1>;
797*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
798*4882a593Smuzhiyun		en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
799*4882a593Smuzhiyun		wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
800*4882a593Smuzhiyun	};
801*4882a593Smuzhiyun};
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun&hsi2c_5 {
804*4882a593Smuzhiyun	status = "okay";
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun	stmfts: touchscreen@49 {
807*4882a593Smuzhiyun		compatible = "st,stmfts";
808*4882a593Smuzhiyun		reg = <0x49>;
809*4882a593Smuzhiyun		interrupt-parent = <&gpa1>;
810*4882a593Smuzhiyun		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
811*4882a593Smuzhiyun		avdd-supply = <&ldo30_reg>;
812*4882a593Smuzhiyun		vdd-supply = <&ldo31_reg>;
813*4882a593Smuzhiyun	};
814*4882a593Smuzhiyun};
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun&hsi2c_7 {
817*4882a593Smuzhiyun	status = "okay";
818*4882a593Smuzhiyun	clock-frequency = <1000000>;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun	sii8620@39 {
821*4882a593Smuzhiyun		reg = <0x39>;
822*4882a593Smuzhiyun		compatible = "sil,sii8620";
823*4882a593Smuzhiyun		cvcc10-supply = <&ldo36_reg>;
824*4882a593Smuzhiyun		iovcc18-supply = <&ldo34_reg>;
825*4882a593Smuzhiyun		interrupt-parent = <&gpf0>;
826*4882a593Smuzhiyun		interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
827*4882a593Smuzhiyun		reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
828*4882a593Smuzhiyun		clocks = <&pmu_system_controller 0>;
829*4882a593Smuzhiyun		clock-names = "xtal";
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun		ports {
832*4882a593Smuzhiyun			#address-cells = <1>;
833*4882a593Smuzhiyun			#size-cells = <0>;
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun			port@0 {
836*4882a593Smuzhiyun				reg = <0>;
837*4882a593Smuzhiyun				mhl_to_hdmi: endpoint {
838*4882a593Smuzhiyun					remote-endpoint = <&hdmi_to_mhl>;
839*4882a593Smuzhiyun				};
840*4882a593Smuzhiyun			};
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun			port@1 {
843*4882a593Smuzhiyun				reg = <1>;
844*4882a593Smuzhiyun				mhl_to_musb_con: endpoint {
845*4882a593Smuzhiyun					remote-endpoint = <&musb_con_to_mhl>;
846*4882a593Smuzhiyun				};
847*4882a593Smuzhiyun			};
848*4882a593Smuzhiyun		};
849*4882a593Smuzhiyun	};
850*4882a593Smuzhiyun};
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun&hsi2c_8 {
853*4882a593Smuzhiyun	status = "okay";
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun	max77843@66 {
856*4882a593Smuzhiyun		compatible = "maxim,max77843";
857*4882a593Smuzhiyun		interrupt-parent = <&gpa1>;
858*4882a593Smuzhiyun		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
859*4882a593Smuzhiyun		reg = <0x66>;
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun		muic: max77843-muic {
862*4882a593Smuzhiyun			compatible = "maxim,max77843-muic";
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun			musb_con: musb_connector {
865*4882a593Smuzhiyun				compatible = "samsung,usb-connector-11pin",
866*4882a593Smuzhiyun					     "usb-b-connector";
867*4882a593Smuzhiyun				label = "micro-USB";
868*4882a593Smuzhiyun				type = "micro";
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun				ports {
871*4882a593Smuzhiyun					#address-cells = <1>;
872*4882a593Smuzhiyun					#size-cells = <0>;
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun					port@3 {
875*4882a593Smuzhiyun						reg = <3>;
876*4882a593Smuzhiyun						musb_con_to_mhl: endpoint {
877*4882a593Smuzhiyun							remote-endpoint = <&mhl_to_musb_con>;
878*4882a593Smuzhiyun						};
879*4882a593Smuzhiyun					};
880*4882a593Smuzhiyun				};
881*4882a593Smuzhiyun			};
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun			ports {
884*4882a593Smuzhiyun				port {
885*4882a593Smuzhiyun					muic_to_usb: endpoint {
886*4882a593Smuzhiyun						remote-endpoint = <&usb_to_muic>;
887*4882a593Smuzhiyun					};
888*4882a593Smuzhiyun				};
889*4882a593Smuzhiyun			};
890*4882a593Smuzhiyun		};
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun		regulators {
893*4882a593Smuzhiyun			compatible = "maxim,max77843-regulator";
894*4882a593Smuzhiyun			safeout1_reg: SAFEOUT1 {
895*4882a593Smuzhiyun				regulator-name = "SAFEOUT1";
896*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
897*4882a593Smuzhiyun				regulator-max-microvolt = <4950000>;
898*4882a593Smuzhiyun			};
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun			safeout2_reg: SAFEOUT2 {
901*4882a593Smuzhiyun				regulator-name = "SAFEOUT2";
902*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
903*4882a593Smuzhiyun				regulator-max-microvolt = <4950000>;
904*4882a593Smuzhiyun			};
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun			charger_reg: CHARGER {
907*4882a593Smuzhiyun				regulator-name = "CHARGER";
908*4882a593Smuzhiyun				regulator-min-microamp = <100000>;
909*4882a593Smuzhiyun				regulator-max-microamp = <3150000>;
910*4882a593Smuzhiyun			};
911*4882a593Smuzhiyun		};
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun		haptic: max77843-haptic {
914*4882a593Smuzhiyun			compatible = "maxim,max77843-haptic";
915*4882a593Smuzhiyun			haptic-supply = <&ldo38_reg>;
916*4882a593Smuzhiyun			pwms = <&pwm 0 33670 0>;
917*4882a593Smuzhiyun			pwm-names = "haptic";
918*4882a593Smuzhiyun		};
919*4882a593Smuzhiyun	};
920*4882a593Smuzhiyun};
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun&hsi2c_11 {
923*4882a593Smuzhiyun	status = "okay";
924*4882a593Smuzhiyun};
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun&i2s0 {
927*4882a593Smuzhiyun	status = "okay";
928*4882a593Smuzhiyun};
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun&i2s1 {
931*4882a593Smuzhiyun	assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
932*4882a593Smuzhiyun	assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
933*4882a593Smuzhiyun	status = "okay";
934*4882a593Smuzhiyun};
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun&mshc_0 {
937*4882a593Smuzhiyun	status = "okay";
938*4882a593Smuzhiyun	mmc-hs200-1_8v;
939*4882a593Smuzhiyun	mmc-hs400-1_8v;
940*4882a593Smuzhiyun	cap-mmc-highspeed;
941*4882a593Smuzhiyun	non-removable;
942*4882a593Smuzhiyun	card-detect-delay = <200>;
943*4882a593Smuzhiyun	samsung,dw-mshc-ciu-div = <3>;
944*4882a593Smuzhiyun	samsung,dw-mshc-sdr-timing = <0 4>;
945*4882a593Smuzhiyun	samsung,dw-mshc-ddr-timing = <0 2>;
946*4882a593Smuzhiyun	samsung,dw-mshc-hs400-timing = <0 3>;
947*4882a593Smuzhiyun	samsung,read-strobe-delay = <90>;
948*4882a593Smuzhiyun	fifo-depth = <0x80>;
949*4882a593Smuzhiyun	pinctrl-names = "default";
950*4882a593Smuzhiyun	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
951*4882a593Smuzhiyun			&sd0_bus8 &sd0_rdqs>;
952*4882a593Smuzhiyun	bus-width = <8>;
953*4882a593Smuzhiyun	assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
954*4882a593Smuzhiyun	assigned-clock-rates = <800000000>;
955*4882a593Smuzhiyun};
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun&mshc_2 {
958*4882a593Smuzhiyun	status = "okay";
959*4882a593Smuzhiyun	cap-sd-highspeed;
960*4882a593Smuzhiyun	disable-wp;
961*4882a593Smuzhiyun	cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
962*4882a593Smuzhiyun	card-detect-delay = <200>;
963*4882a593Smuzhiyun	samsung,dw-mshc-ciu-div = <3>;
964*4882a593Smuzhiyun	samsung,dw-mshc-sdr-timing = <0 4>;
965*4882a593Smuzhiyun	samsung,dw-mshc-ddr-timing = <0 2>;
966*4882a593Smuzhiyun	fifo-depth = <0x80>;
967*4882a593Smuzhiyun	pinctrl-names = "default";
968*4882a593Smuzhiyun	pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
969*4882a593Smuzhiyun	bus-width = <4>;
970*4882a593Smuzhiyun};
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun&ppmu_d0_general {
973*4882a593Smuzhiyun	status = "okay";
974*4882a593Smuzhiyun	events {
975*4882a593Smuzhiyun		ppmu_event0_d0_general: ppmu-event0-d0-general {
976*4882a593Smuzhiyun			event-name = "ppmu-event0-d0-general";
977*4882a593Smuzhiyun		};
978*4882a593Smuzhiyun	};
979*4882a593Smuzhiyun};
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun&ppmu_d1_general {
982*4882a593Smuzhiyun	status = "okay";
983*4882a593Smuzhiyun	events {
984*4882a593Smuzhiyun		ppmu_event0_d1_general: ppmu-event0-d1-general {
985*4882a593Smuzhiyun		       event-name = "ppmu-event0-d1-general";
986*4882a593Smuzhiyun	       };
987*4882a593Smuzhiyun       };
988*4882a593Smuzhiyun};
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun&pinctrl_alive {
991*4882a593Smuzhiyun	pinctrl-names = "default";
992*4882a593Smuzhiyun	pinctrl-0 = <&initial_alive>;
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun	initial_alive: initial-state {
995*4882a593Smuzhiyun		PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
996*4882a593Smuzhiyun		PIN(INPUT, gpa0-1, NONE, FAST_SR1);
997*4882a593Smuzhiyun		PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
998*4882a593Smuzhiyun		PIN(INPUT, gpa0-3, NONE, FAST_SR1);
999*4882a593Smuzhiyun		PIN(INPUT, gpa0-4, NONE, FAST_SR1);
1000*4882a593Smuzhiyun		PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
1001*4882a593Smuzhiyun		PIN(INPUT, gpa0-6, NONE, FAST_SR1);
1002*4882a593Smuzhiyun		PIN(INPUT, gpa0-7, NONE, FAST_SR1);
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun		PIN(INPUT, gpa1-0, UP, FAST_SR1);
1005*4882a593Smuzhiyun		PIN(INPUT, gpa1-1, UP, FAST_SR1);
1006*4882a593Smuzhiyun		PIN(INPUT, gpa1-2, NONE, FAST_SR1);
1007*4882a593Smuzhiyun		PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
1008*4882a593Smuzhiyun		PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
1009*4882a593Smuzhiyun		PIN(INPUT, gpa1-5, NONE, FAST_SR1);
1010*4882a593Smuzhiyun		PIN(INPUT, gpa1-6, NONE, FAST_SR1);
1011*4882a593Smuzhiyun		PIN(INPUT, gpa1-7, NONE, FAST_SR1);
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun		PIN(INPUT, gpa2-0, NONE, FAST_SR1);
1014*4882a593Smuzhiyun		PIN(INPUT, gpa2-1, NONE, FAST_SR1);
1015*4882a593Smuzhiyun		PIN(INPUT, gpa2-2, NONE, FAST_SR1);
1016*4882a593Smuzhiyun		PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
1017*4882a593Smuzhiyun		PIN(INPUT, gpa2-4, NONE, FAST_SR1);
1018*4882a593Smuzhiyun		PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
1019*4882a593Smuzhiyun		PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
1020*4882a593Smuzhiyun		PIN(INPUT, gpa2-7, NONE, FAST_SR1);
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun		PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
1023*4882a593Smuzhiyun		PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
1024*4882a593Smuzhiyun		PIN(INPUT, gpa3-2, NONE, FAST_SR1);
1025*4882a593Smuzhiyun		PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
1026*4882a593Smuzhiyun		PIN(INPUT, gpa3-4, NONE, FAST_SR1);
1027*4882a593Smuzhiyun		PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
1028*4882a593Smuzhiyun		PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
1029*4882a593Smuzhiyun		PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun		PIN(INPUT, gpf1-0, NONE, FAST_SR1);
1032*4882a593Smuzhiyun		PIN(INPUT, gpf1-1, NONE, FAST_SR1);
1033*4882a593Smuzhiyun		PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
1034*4882a593Smuzhiyun		PIN(INPUT, gpf1-4, UP, FAST_SR1);
1035*4882a593Smuzhiyun		PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
1036*4882a593Smuzhiyun		PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
1037*4882a593Smuzhiyun		PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun		PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
1040*4882a593Smuzhiyun		PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
1041*4882a593Smuzhiyun		PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
1042*4882a593Smuzhiyun		PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun		PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
1045*4882a593Smuzhiyun		PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
1046*4882a593Smuzhiyun		PIN(INPUT, gpf3-2, NONE, FAST_SR1);
1047*4882a593Smuzhiyun		PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun		PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
1050*4882a593Smuzhiyun		PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
1051*4882a593Smuzhiyun		PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
1052*4882a593Smuzhiyun		PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
1053*4882a593Smuzhiyun		PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
1054*4882a593Smuzhiyun		PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
1055*4882a593Smuzhiyun		PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
1056*4882a593Smuzhiyun		PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun		PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
1059*4882a593Smuzhiyun		PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
1060*4882a593Smuzhiyun		PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
1061*4882a593Smuzhiyun		PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
1062*4882a593Smuzhiyun		PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
1063*4882a593Smuzhiyun		PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
1064*4882a593Smuzhiyun		PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
1065*4882a593Smuzhiyun		PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
1066*4882a593Smuzhiyun	};
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun	te_irq: te_irq {
1069*4882a593Smuzhiyun		samsung,pins = "gpf1-3";
1070*4882a593Smuzhiyun		samsung,pin-function = <0xf>;
1071*4882a593Smuzhiyun	};
1072*4882a593Smuzhiyun};
1073*4882a593Smuzhiyun
1074*4882a593Smuzhiyun&pinctrl_cpif {
1075*4882a593Smuzhiyun	pinctrl-names = "default";
1076*4882a593Smuzhiyun	pinctrl-0 = <&initial_cpif>;
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun	initial_cpif: initial-state {
1079*4882a593Smuzhiyun		PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
1080*4882a593Smuzhiyun		PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
1081*4882a593Smuzhiyun	};
1082*4882a593Smuzhiyun};
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun&pinctrl_ese {
1085*4882a593Smuzhiyun	pinctrl-names = "default";
1086*4882a593Smuzhiyun	pinctrl-0 = <&initial_ese>;
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun	initial_ese: initial-state {
1089*4882a593Smuzhiyun		PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
1090*4882a593Smuzhiyun		PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
1091*4882a593Smuzhiyun		PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
1092*4882a593Smuzhiyun	};
1093*4882a593Smuzhiyun};
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun&pinctrl_fsys {
1096*4882a593Smuzhiyun	pinctrl-names = "default";
1097*4882a593Smuzhiyun	pinctrl-0 = <&initial_fsys>;
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun	initial_fsys: initial-state {
1100*4882a593Smuzhiyun		PIN(INPUT, gpr3-0, NONE, FAST_SR1);
1101*4882a593Smuzhiyun		PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
1102*4882a593Smuzhiyun		PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
1103*4882a593Smuzhiyun		PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
1104*4882a593Smuzhiyun		PIN(INPUT, gpr3-7, NONE, FAST_SR1);
1105*4882a593Smuzhiyun	};
1106*4882a593Smuzhiyun};
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun&pinctrl_imem {
1109*4882a593Smuzhiyun	pinctrl-names = "default";
1110*4882a593Smuzhiyun	pinctrl-0 = <&initial_imem>;
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun	initial_imem: initial-state {
1113*4882a593Smuzhiyun		PIN(INPUT, gpf0-0, UP, FAST_SR1);
1114*4882a593Smuzhiyun		PIN(INPUT, gpf0-1, UP, FAST_SR1);
1115*4882a593Smuzhiyun		PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
1116*4882a593Smuzhiyun		PIN(INPUT, gpf0-3, UP, FAST_SR1);
1117*4882a593Smuzhiyun		PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
1118*4882a593Smuzhiyun		PIN(INPUT, gpf0-5, NONE, FAST_SR1);
1119*4882a593Smuzhiyun		PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
1120*4882a593Smuzhiyun		PIN(INPUT, gpf0-7, UP, FAST_SR1);
1121*4882a593Smuzhiyun	};
1122*4882a593Smuzhiyun};
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun&pinctrl_nfc {
1125*4882a593Smuzhiyun	pinctrl-names = "default";
1126*4882a593Smuzhiyun	pinctrl-0 = <&initial_nfc>;
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun	initial_nfc: initial-state {
1129*4882a593Smuzhiyun		PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
1130*4882a593Smuzhiyun	};
1131*4882a593Smuzhiyun};
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun&pinctrl_peric {
1134*4882a593Smuzhiyun	pinctrl-names = "default";
1135*4882a593Smuzhiyun	pinctrl-0 = <&initial_peric>;
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun	initial_peric: initial-state {
1138*4882a593Smuzhiyun		PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
1139*4882a593Smuzhiyun		PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
1140*4882a593Smuzhiyun		PIN(INPUT, gpv7-2, NONE, FAST_SR1);
1141*4882a593Smuzhiyun		PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
1142*4882a593Smuzhiyun		PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
1143*4882a593Smuzhiyun		PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun		PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun		PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
1148*4882a593Smuzhiyun		PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
1149*4882a593Smuzhiyun		PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun		PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun		PIN(INPUT, gpc3-4, NONE, FAST_SR1);
1154*4882a593Smuzhiyun		PIN(INPUT, gpc3-5, NONE, FAST_SR1);
1155*4882a593Smuzhiyun		PIN(INPUT, gpc3-6, NONE, FAST_SR1);
1156*4882a593Smuzhiyun		PIN(INPUT, gpc3-7, NONE, FAST_SR1);
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun		PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
1159*4882a593Smuzhiyun		PIN(2, gpg0-1, DOWN, FAST_SR1);
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun		PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun		PIN(INPUT, gpd4-0, NONE, FAST_SR1);
1164*4882a593Smuzhiyun		PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
1165*4882a593Smuzhiyun		PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
1166*4882a593Smuzhiyun		PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
1167*4882a593Smuzhiyun		PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun		PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun		PIN(INPUT, gpd8-1, UP, FAST_SR1);
1172*4882a593Smuzhiyun
1173*4882a593Smuzhiyun		PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
1174*4882a593Smuzhiyun		PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
1175*4882a593Smuzhiyun		PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
1176*4882a593Smuzhiyun		PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
1177*4882a593Smuzhiyun		PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun		PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
1180*4882a593Smuzhiyun		PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun		PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
1183*4882a593Smuzhiyun		PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
1184*4882a593Smuzhiyun		PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
1185*4882a593Smuzhiyun	};
1186*4882a593Smuzhiyun};
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun&pinctrl_touch {
1189*4882a593Smuzhiyun	pinctrl-names = "default";
1190*4882a593Smuzhiyun	pinctrl-0 = <&initial_touch>;
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun	initial_touch: initial-state {
1193*4882a593Smuzhiyun		PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
1194*4882a593Smuzhiyun	};
1195*4882a593Smuzhiyun};
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun&pwm {
1198*4882a593Smuzhiyun	pinctrl-0 = <&pwm0_out>;
1199*4882a593Smuzhiyun	pinctrl-names = "default";
1200*4882a593Smuzhiyun	status = "okay";
1201*4882a593Smuzhiyun};
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun&mic {
1204*4882a593Smuzhiyun	status = "okay";
1205*4882a593Smuzhiyun};
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun&pmu_system_controller {
1208*4882a593Smuzhiyun	assigned-clocks = <&pmu_system_controller 0>;
1209*4882a593Smuzhiyun	assigned-clock-parents = <&xxti>;
1210*4882a593Smuzhiyun};
1211*4882a593Smuzhiyun
1212*4882a593Smuzhiyun&serial_1 {
1213*4882a593Smuzhiyun	status = "okay";
1214*4882a593Smuzhiyun};
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun&serial_3 {
1217*4882a593Smuzhiyun	status = "okay";
1218*4882a593Smuzhiyun
1219*4882a593Smuzhiyun	bluetooth {
1220*4882a593Smuzhiyun		compatible = "brcm,bcm43438-bt";
1221*4882a593Smuzhiyun		max-speed = <3000000>;
1222*4882a593Smuzhiyun		shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
1223*4882a593Smuzhiyun		device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
1224*4882a593Smuzhiyun		host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
1225*4882a593Smuzhiyun		clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
1226*4882a593Smuzhiyun		clock-names = "extclk";
1227*4882a593Smuzhiyun	};
1228*4882a593Smuzhiyun};
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun&spi_1 {
1231*4882a593Smuzhiyun	cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1232*4882a593Smuzhiyun	status = "okay";
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun	wm5110: wm5110-codec@0 {
1235*4882a593Smuzhiyun		compatible = "wlf,wm5110";
1236*4882a593Smuzhiyun		reg = <0x0>;
1237*4882a593Smuzhiyun		spi-max-frequency = <20000000>;
1238*4882a593Smuzhiyun		interrupt-parent = <&gpa0>;
1239*4882a593Smuzhiyun		interrupts = <4 IRQ_TYPE_NONE>;
1240*4882a593Smuzhiyun		clocks = <&pmu_system_controller 0>,
1241*4882a593Smuzhiyun			<&s2mps13_osc S2MPS11_CLK_BT>;
1242*4882a593Smuzhiyun		clock-names = "mclk1", "mclk2";
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun		gpio-controller;
1245*4882a593Smuzhiyun		#gpio-cells = <2>;
1246*4882a593Smuzhiyun
1247*4882a593Smuzhiyun		wlf,micd-detect-debounce = <300>;
1248*4882a593Smuzhiyun		wlf,micd-bias-start-time = <0x1>;
1249*4882a593Smuzhiyun		wlf,micd-rate = <0x7>;
1250*4882a593Smuzhiyun		wlf,micd-dbtime = <0x1>;
1251*4882a593Smuzhiyun		wlf,micd-force-micbias;
1252*4882a593Smuzhiyun		wlf,micd-configs = <0x0 1 0>;
1253*4882a593Smuzhiyun		wlf,hpdet-channel = <1>;
1254*4882a593Smuzhiyun		wlf,gpsw = <0x1>;
1255*4882a593Smuzhiyun		wlf,inmode = <2 0 2 0>;
1256*4882a593Smuzhiyun
1257*4882a593Smuzhiyun		wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1258*4882a593Smuzhiyun		wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun		/* core supplies */
1261*4882a593Smuzhiyun		AVDD-supply = <&ldo18_reg>;
1262*4882a593Smuzhiyun		DBVDD1-supply = <&ldo18_reg>;
1263*4882a593Smuzhiyun		CPVDD-supply = <&ldo18_reg>;
1264*4882a593Smuzhiyun		DBVDD2-supply = <&ldo18_reg>;
1265*4882a593Smuzhiyun		DBVDD3-supply = <&ldo18_reg>;
1266*4882a593Smuzhiyun
1267*4882a593Smuzhiyun		controller-data {
1268*4882a593Smuzhiyun			samsung,spi-feedback-delay = <0>;
1269*4882a593Smuzhiyun		};
1270*4882a593Smuzhiyun	};
1271*4882a593Smuzhiyun};
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun&spi_3 {
1274*4882a593Smuzhiyun	status = "okay";
1275*4882a593Smuzhiyun	no-cs-readback;
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun	irled@0 {
1278*4882a593Smuzhiyun		compatible = "ir-spi-led";
1279*4882a593Smuzhiyun		reg = <0x0>;
1280*4882a593Smuzhiyun		spi-max-frequency = <5000000>;
1281*4882a593Smuzhiyun		power-supply = <&irda_regulator>;
1282*4882a593Smuzhiyun		duty-cycle = <60>;
1283*4882a593Smuzhiyun		led-active-low;
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun		controller-data {
1286*4882a593Smuzhiyun			samsung,spi-feedback-delay = <0>;
1287*4882a593Smuzhiyun		};
1288*4882a593Smuzhiyun	};
1289*4882a593Smuzhiyun};
1290*4882a593Smuzhiyun
1291*4882a593Smuzhiyun&timer {
1292*4882a593Smuzhiyun	clock-frequency = <24000000>;
1293*4882a593Smuzhiyun};
1294*4882a593Smuzhiyun
1295*4882a593Smuzhiyun&tmu_atlas0 {
1296*4882a593Smuzhiyun	vtmu-supply = <&ldo3_reg>;
1297*4882a593Smuzhiyun	status = "okay";
1298*4882a593Smuzhiyun};
1299*4882a593Smuzhiyun
1300*4882a593Smuzhiyun&tmu_apollo {
1301*4882a593Smuzhiyun	vtmu-supply = <&ldo3_reg>;
1302*4882a593Smuzhiyun	status = "okay";
1303*4882a593Smuzhiyun};
1304*4882a593Smuzhiyun
1305*4882a593Smuzhiyun&tmu_g3d {
1306*4882a593Smuzhiyun	vtmu-supply = <&ldo3_reg>;
1307*4882a593Smuzhiyun	status = "okay";
1308*4882a593Smuzhiyun};
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun&usbdrd30 {
1311*4882a593Smuzhiyun	vdd33-supply = <&ldo10_reg>;
1312*4882a593Smuzhiyun	vdd10-supply = <&ldo6_reg>;
1313*4882a593Smuzhiyun	status = "okay";
1314*4882a593Smuzhiyun};
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun&usbdrd_dwc3 {
1317*4882a593Smuzhiyun	dr_mode = "otg";
1318*4882a593Smuzhiyun};
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun&usbdrd30_phy {
1321*4882a593Smuzhiyun	vbus-supply = <&safeout1_reg>;
1322*4882a593Smuzhiyun	status = "okay";
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun	port {
1325*4882a593Smuzhiyun		usb_to_muic: endpoint {
1326*4882a593Smuzhiyun			remote-endpoint = <&muic_to_usb>;
1327*4882a593Smuzhiyun		};
1328*4882a593Smuzhiyun	};
1329*4882a593Smuzhiyun};
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun&xxti {
1332*4882a593Smuzhiyun	clock-frequency = <24000000>;
1333*4882a593Smuzhiyun};
1334