xref: /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/broadcom/stingray/stingray-pinctrl.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun *  BSD LICENSE
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun *  Copyright(c) 2016-2017 Broadcom.  All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun *  Redistribution and use in source and binary forms, with or without
7*4882a593Smuzhiyun *  modification, are permitted provided that the following conditions
8*4882a593Smuzhiyun *  are met:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun *    * Redistributions of source code must retain the above copyright
11*4882a593Smuzhiyun *      notice, this list of conditions and the following disclaimer.
12*4882a593Smuzhiyun *    * Redistributions in binary form must reproduce the above copyright
13*4882a593Smuzhiyun *      notice, this list of conditions and the following disclaimer in
14*4882a593Smuzhiyun *      the documentation and/or other materials provided with the
15*4882a593Smuzhiyun *      distribution.
16*4882a593Smuzhiyun *    * Neither the name of Broadcom nor the names of its
17*4882a593Smuzhiyun *      contributors may be used to endorse or promote products derived
18*4882a593Smuzhiyun *      from this software without specific prior written permission.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21*4882a593Smuzhiyun *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22*4882a593Smuzhiyun *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23*4882a593Smuzhiyun *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24*4882a593Smuzhiyun *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25*4882a593Smuzhiyun *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26*4882a593Smuzhiyun *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27*4882a593Smuzhiyun *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28*4882a593Smuzhiyun *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29*4882a593Smuzhiyun *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30*4882a593Smuzhiyun *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun#include <dt-bindings/pinctrl/brcm,pinctrl-stingray.h>
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		pinconf: pinconf@140000 {
36*4882a593Smuzhiyun			compatible = "pinconf-single";
37*4882a593Smuzhiyun			reg = <0x00140000 0x250>;
38*4882a593Smuzhiyun			pinctrl-single,register-width = <32>;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun			/* pinconf functions */
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		pinmux: pinmux@14029c {
44*4882a593Smuzhiyun			compatible = "pinctrl-single";
45*4882a593Smuzhiyun			reg = <0x0014029c 0x26c>;
46*4882a593Smuzhiyun			#address-cells = <1>;
47*4882a593Smuzhiyun			#size-cells = <1>;
48*4882a593Smuzhiyun			pinctrl-single,register-width = <32>;
49*4882a593Smuzhiyun			pinctrl-single,function-mask = <0xf>;
50*4882a593Smuzhiyun			pinctrl-single,gpio-range = <
51*4882a593Smuzhiyun				&range 0  91 MODE_GPIO
52*4882a593Smuzhiyun				&range 95 60 MODE_GPIO
53*4882a593Smuzhiyun				>;
54*4882a593Smuzhiyun			range: gpio-range {
55*4882a593Smuzhiyun				#pinctrl-single,gpio-range-cells = <3>;
56*4882a593Smuzhiyun			};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun			/* pinctrl functions */
59*4882a593Smuzhiyun			tsio_pins: pinmux_gpio_14 {
60*4882a593Smuzhiyun				pinctrl-single,pins = <
61*4882a593Smuzhiyun					0x038 MODE_NITRO /* tsio_0 */
62*4882a593Smuzhiyun					0x03c MODE_NITRO /* tsio_1 */
63*4882a593Smuzhiyun				>;
64*4882a593Smuzhiyun			};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun			nor_pins: pinmux_pnor_adv_n {
67*4882a593Smuzhiyun				pinctrl-single,pins = <
68*4882a593Smuzhiyun					0x0ac MODE_PNOR /* nand_ce1_n */
69*4882a593Smuzhiyun					0x0b0 MODE_PNOR /* nand_ce0_n */
70*4882a593Smuzhiyun					0x0b4 MODE_PNOR /* nand_we_n */
71*4882a593Smuzhiyun					0x0b8 MODE_PNOR /* nand_wp_n */
72*4882a593Smuzhiyun					0x0bc MODE_PNOR /* nand_re_n */
73*4882a593Smuzhiyun					0x0c0 MODE_PNOR /* nand_rdy_bsy_n */
74*4882a593Smuzhiyun					0x0c4 MODE_PNOR /* nand_io0_0 */
75*4882a593Smuzhiyun					0x0c8 MODE_PNOR /* nand_io1_0 */
76*4882a593Smuzhiyun					0x0cc MODE_PNOR /* nand_io2_0 */
77*4882a593Smuzhiyun					0x0d0 MODE_PNOR /* nand_io3_0 */
78*4882a593Smuzhiyun					0x0d4 MODE_PNOR /* nand_io4_0 */
79*4882a593Smuzhiyun					0x0d8 MODE_PNOR /* nand_io5_0 */
80*4882a593Smuzhiyun					0x0dc MODE_PNOR /* nand_io6_0 */
81*4882a593Smuzhiyun					0x0e0 MODE_PNOR /* nand_io7_0 */
82*4882a593Smuzhiyun					0x0e4 MODE_PNOR /* nand_io8_0 */
83*4882a593Smuzhiyun					0x0e8 MODE_PNOR /* nand_io9_0 */
84*4882a593Smuzhiyun					0x0ec MODE_PNOR /* nand_io10_0 */
85*4882a593Smuzhiyun					0x0f0 MODE_PNOR /* nand_io11_0 */
86*4882a593Smuzhiyun					0x0f4 MODE_PNOR /* nand_io12_0 */
87*4882a593Smuzhiyun					0x0f8 MODE_PNOR /* nand_io13_0 */
88*4882a593Smuzhiyun					0x0fc MODE_PNOR /* nand_io14_0 */
89*4882a593Smuzhiyun					0x100 MODE_PNOR /* nand_io15_0 */
90*4882a593Smuzhiyun					0x104 MODE_PNOR /* nand_ale_0 */
91*4882a593Smuzhiyun					0x108 MODE_PNOR /* nand_cle_0 */
92*4882a593Smuzhiyun					0x040 MODE_PNOR /* pnor_adv_n */
93*4882a593Smuzhiyun					0x044 MODE_PNOR /* pnor_baa_n */
94*4882a593Smuzhiyun					0x048 MODE_PNOR /* pnor_bls_0_n */
95*4882a593Smuzhiyun					0x04c MODE_PNOR /* pnor_bls_1_n */
96*4882a593Smuzhiyun					0x050 MODE_PNOR /* pnor_cre */
97*4882a593Smuzhiyun					0x054 MODE_PNOR /* pnor_cs_2_n */
98*4882a593Smuzhiyun					0x058 MODE_PNOR /* pnor_cs_1_n */
99*4882a593Smuzhiyun					0x05c MODE_PNOR /* pnor_cs_0_n */
100*4882a593Smuzhiyun					0x060 MODE_PNOR /* pnor_we_n */
101*4882a593Smuzhiyun					0x064 MODE_PNOR /* pnor_oe_n */
102*4882a593Smuzhiyun					0x068 MODE_PNOR /* pnor_intr */
103*4882a593Smuzhiyun					0x06c MODE_PNOR /* pnor_dat_0 */
104*4882a593Smuzhiyun					0x070 MODE_PNOR /* pnor_dat_1 */
105*4882a593Smuzhiyun					0x074 MODE_PNOR /* pnor_dat_2 */
106*4882a593Smuzhiyun					0x078 MODE_PNOR /* pnor_dat_3 */
107*4882a593Smuzhiyun					0x07c MODE_PNOR /* pnor_dat_4 */
108*4882a593Smuzhiyun					0x080 MODE_PNOR /* pnor_dat_5 */
109*4882a593Smuzhiyun					0x084 MODE_PNOR /* pnor_dat_6 */
110*4882a593Smuzhiyun					0x088 MODE_PNOR /* pnor_dat_7 */
111*4882a593Smuzhiyun					0x08c MODE_PNOR /* pnor_dat_8 */
112*4882a593Smuzhiyun					0x090 MODE_PNOR /* pnor_dat_9 */
113*4882a593Smuzhiyun					0x094 MODE_PNOR /* pnor_dat_10 */
114*4882a593Smuzhiyun					0x098 MODE_PNOR /* pnor_dat_11 */
115*4882a593Smuzhiyun					0x09c MODE_PNOR /* pnor_dat_12 */
116*4882a593Smuzhiyun					0x0a0 MODE_PNOR /* pnor_dat_13 */
117*4882a593Smuzhiyun					0x0a4 MODE_PNOR /* pnor_dat_14 */
118*4882a593Smuzhiyun					0x0a8 MODE_PNOR /* pnor_dat_15 */
119*4882a593Smuzhiyun				>;
120*4882a593Smuzhiyun			};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun			nand_pins: pinmux_nand_ce1_n {
123*4882a593Smuzhiyun				pinctrl-single,pins = <
124*4882a593Smuzhiyun					0x0ac MODE_NAND /* nand_ce1_n */
125*4882a593Smuzhiyun					0x0b0 MODE_NAND /* nand_ce0_n */
126*4882a593Smuzhiyun					0x0b4 MODE_NAND /* nand_we_n */
127*4882a593Smuzhiyun					0x0b8 MODE_NAND /* nand_wp_n */
128*4882a593Smuzhiyun					0x0bc MODE_NAND /* nand_re_n */
129*4882a593Smuzhiyun					0x0c0 MODE_NAND /* nand_rdy_bsy_n */
130*4882a593Smuzhiyun					0x0c4 MODE_NAND /* nand_io0_0 */
131*4882a593Smuzhiyun					0x0c8 MODE_NAND /* nand_io1_0 */
132*4882a593Smuzhiyun					0x0cc MODE_NAND /* nand_io2_0 */
133*4882a593Smuzhiyun					0x0d0 MODE_NAND /* nand_io3_0 */
134*4882a593Smuzhiyun					0x0d4 MODE_NAND /* nand_io4_0 */
135*4882a593Smuzhiyun					0x0d8 MODE_NAND /* nand_io5_0 */
136*4882a593Smuzhiyun					0x0dc MODE_NAND /* nand_io6_0 */
137*4882a593Smuzhiyun					0x0e0 MODE_NAND /* nand_io7_0 */
138*4882a593Smuzhiyun					0x0e4 MODE_NAND /* nand_io8_0 */
139*4882a593Smuzhiyun					0x0e8 MODE_NAND /* nand_io9_0 */
140*4882a593Smuzhiyun					0x0ec MODE_NAND /* nand_io10_0 */
141*4882a593Smuzhiyun					0x0f0 MODE_NAND /* nand_io11_0 */
142*4882a593Smuzhiyun					0x0f4 MODE_NAND /* nand_io12_0 */
143*4882a593Smuzhiyun					0x0f8 MODE_NAND /* nand_io13_0 */
144*4882a593Smuzhiyun					0x0fc MODE_NAND /* nand_io14_0 */
145*4882a593Smuzhiyun					0x100 MODE_NAND /* nand_io15_0 */
146*4882a593Smuzhiyun					0x104 MODE_NAND /* nand_ale_0 */
147*4882a593Smuzhiyun					0x108 MODE_NAND /* nand_cle_0 */
148*4882a593Smuzhiyun				>;
149*4882a593Smuzhiyun			};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun			pwm0_pins: pinmux_pwm_0 {
152*4882a593Smuzhiyun				pinctrl-single,pins = <
153*4882a593Smuzhiyun					0x10c MODE_NITRO
154*4882a593Smuzhiyun				>;
155*4882a593Smuzhiyun			};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun			pwm1_pins: pinmux_pwm_1 {
158*4882a593Smuzhiyun				pinctrl-single,pins = <
159*4882a593Smuzhiyun					0x110 MODE_NITRO
160*4882a593Smuzhiyun				>;
161*4882a593Smuzhiyun			};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			pwm2_pins: pinmux_pwm_2 {
164*4882a593Smuzhiyun				pinctrl-single,pins = <
165*4882a593Smuzhiyun					0x114 MODE_NITRO
166*4882a593Smuzhiyun				>;
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun			pwm3_pins: pinmux_pwm_3 {
170*4882a593Smuzhiyun				pinctrl-single,pins = <
171*4882a593Smuzhiyun					0x118 MODE_NITRO
172*4882a593Smuzhiyun				>;
173*4882a593Smuzhiyun			};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun			dbu_rxd_pins: pinmux_uart1_sin_nitro {
176*4882a593Smuzhiyun				pinctrl-single,pins = <
177*4882a593Smuzhiyun					0x11c MODE_NITRO /* dbu_rxd */
178*4882a593Smuzhiyun					0x120 MODE_NITRO /* dbu_txd */
179*4882a593Smuzhiyun				>;
180*4882a593Smuzhiyun			};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun			uart1_pins: pinmux_uart1_sin_nand {
183*4882a593Smuzhiyun				pinctrl-single,pins = <
184*4882a593Smuzhiyun					0x11c MODE_NAND /* uart1_sin */
185*4882a593Smuzhiyun					0x120 MODE_NAND /* uart1_out */
186*4882a593Smuzhiyun				>;
187*4882a593Smuzhiyun			};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun			uart2_pins: pinmux_uart2_sin {
190*4882a593Smuzhiyun				pinctrl-single,pins = <
191*4882a593Smuzhiyun					0x124 MODE_NITRO /* uart2_sin */
192*4882a593Smuzhiyun					0x128 MODE_NITRO /* uart2_out */
193*4882a593Smuzhiyun				>;
194*4882a593Smuzhiyun			};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun			uart3_pins: pinmux_uart3_sin {
197*4882a593Smuzhiyun				pinctrl-single,pins = <
198*4882a593Smuzhiyun					0x12c MODE_NITRO /* uart3_sin */
199*4882a593Smuzhiyun					0x130 MODE_NITRO /* uart3_out */
200*4882a593Smuzhiyun				>;
201*4882a593Smuzhiyun			};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun			i2s_pins: pinmux_i2s_bitclk {
204*4882a593Smuzhiyun				pinctrl-single,pins = <
205*4882a593Smuzhiyun					0x134 MODE_NITRO /* i2s_bitclk */
206*4882a593Smuzhiyun					0x138 MODE_NITRO /* i2s_sdout */
207*4882a593Smuzhiyun					0x13c MODE_NITRO /* i2s_sdin */
208*4882a593Smuzhiyun					0x140 MODE_NITRO /* i2s_ws */
209*4882a593Smuzhiyun					0x144 MODE_NITRO /* i2s_mclk */
210*4882a593Smuzhiyun					0x148 MODE_NITRO /* i2s_spdif_out */
211*4882a593Smuzhiyun				>;
212*4882a593Smuzhiyun			};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun			qspi_pins: pinumx_qspi_hold_n {
215*4882a593Smuzhiyun				pinctrl-single,pins = <
216*4882a593Smuzhiyun					0x14c MODE_NAND /* qspi_hold_n */
217*4882a593Smuzhiyun					0x150 MODE_NAND /* qspi_wp_n */
218*4882a593Smuzhiyun					0x154 MODE_NAND /* qspi_sck */
219*4882a593Smuzhiyun					0x158 MODE_NAND /* qspi_cs_n */
220*4882a593Smuzhiyun					0x15c MODE_NAND /* qspi_mosi */
221*4882a593Smuzhiyun					0x160 MODE_NAND /* qspi_miso */
222*4882a593Smuzhiyun				>;
223*4882a593Smuzhiyun			};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun			mdio_pins: pinumx_ext_mdio {
226*4882a593Smuzhiyun				pinctrl-single,pins = <
227*4882a593Smuzhiyun					0x164 MODE_NITRO /* ext_mdio */
228*4882a593Smuzhiyun					0x168 MODE_NITRO /* ext_mdc */
229*4882a593Smuzhiyun				>;
230*4882a593Smuzhiyun			};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun			i2c0_pins: pinmux_i2c0_sda {
233*4882a593Smuzhiyun				pinctrl-single,pins = <
234*4882a593Smuzhiyun					0x16c MODE_NITRO /* i2c0_sda */
235*4882a593Smuzhiyun					0x170 MODE_NITRO /* i2c0_scl */
236*4882a593Smuzhiyun				>;
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun			i2c1_pins: pinmux_i2c1_sda {
240*4882a593Smuzhiyun				pinctrl-single,pins = <
241*4882a593Smuzhiyun					0x174 MODE_NITRO /* i2c1_sda */
242*4882a593Smuzhiyun					0x178 MODE_NITRO /* i2c1_scl */
243*4882a593Smuzhiyun				>;
244*4882a593Smuzhiyun			};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun			sdio0_pins: pinmux_sdio0_cd_l {
247*4882a593Smuzhiyun				pinctrl-single,pins = <
248*4882a593Smuzhiyun					0x17c MODE_NITRO /* sdio0_cd_l */
249*4882a593Smuzhiyun					0x180 MODE_NITRO /* sdio0_clk_sdcard */
250*4882a593Smuzhiyun					0x184 MODE_NITRO /* sdio0_data0 */
251*4882a593Smuzhiyun					0x188 MODE_NITRO /* sdio0_data1 */
252*4882a593Smuzhiyun					0x18c MODE_NITRO /* sdio0_data2 */
253*4882a593Smuzhiyun					0x190 MODE_NITRO /* sdio0_data3 */
254*4882a593Smuzhiyun					0x194 MODE_NITRO /* sdio0_data4 */
255*4882a593Smuzhiyun					0x198 MODE_NITRO /* sdio0_data5 */
256*4882a593Smuzhiyun					0x19c MODE_NITRO /* sdio0_data6 */
257*4882a593Smuzhiyun					0x1a0 MODE_NITRO /* sdio0_data7 */
258*4882a593Smuzhiyun					0x1a4 MODE_NITRO /* sdio0_cmd */
259*4882a593Smuzhiyun					0x1a8 MODE_NITRO /* sdio0_emmc_rst_n */
260*4882a593Smuzhiyun					0x1ac MODE_NITRO /* sdio0_led_on */
261*4882a593Smuzhiyun					0x1b0 MODE_NITRO /* sdio0_wp */
262*4882a593Smuzhiyun				>;
263*4882a593Smuzhiyun			};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun			sdio1_pins: pinmux_sdio1_cd_l {
266*4882a593Smuzhiyun				pinctrl-single,pins = <
267*4882a593Smuzhiyun					0x1b4 MODE_NITRO /* sdio1_cd_l */
268*4882a593Smuzhiyun					0x1b8 MODE_NITRO /* sdio1_clk_sdcard */
269*4882a593Smuzhiyun					0x1bc MODE_NITRO /* sdio1_data0 */
270*4882a593Smuzhiyun					0x1c0 MODE_NITRO /* sdio1_data1 */
271*4882a593Smuzhiyun					0x1c4 MODE_NITRO /* sdio1_data2 */
272*4882a593Smuzhiyun					0x1c8 MODE_NITRO /* sdio1_data3 */
273*4882a593Smuzhiyun					0x1cc MODE_NITRO /* sdio1_data4 */
274*4882a593Smuzhiyun					0x1d0 MODE_NITRO /* sdio1_data5 */
275*4882a593Smuzhiyun					0x1d4 MODE_NITRO /* sdio1_data6 */
276*4882a593Smuzhiyun					0x1d8 MODE_NITRO /* sdio1_data7 */
277*4882a593Smuzhiyun					0x1dc MODE_NITRO /* sdio1_cmd */
278*4882a593Smuzhiyun					0x1e0 MODE_NITRO /* sdio1_emmc_rst_n */
279*4882a593Smuzhiyun					0x1e4 MODE_NITRO /* sdio1_led_on */
280*4882a593Smuzhiyun					0x1e8 MODE_NITRO /* sdio1_wp */
281*4882a593Smuzhiyun				>;
282*4882a593Smuzhiyun			};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun			spi0_pins: pinmux_spi0_sck_nand {
285*4882a593Smuzhiyun				pinctrl-single,pins = <
286*4882a593Smuzhiyun					0x1ec MODE_NITRO /* spi0_sck */
287*4882a593Smuzhiyun					0x1f0 MODE_NITRO /* spi0_rxd */
288*4882a593Smuzhiyun					0x1f4 MODE_NITRO /* spi0_fss */
289*4882a593Smuzhiyun					0x1f8 MODE_NITRO /* spi0_txd */
290*4882a593Smuzhiyun				>;
291*4882a593Smuzhiyun			};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun			spi1_pins: pinmux_spi1_sck_nand {
294*4882a593Smuzhiyun				pinctrl-single,pins = <
295*4882a593Smuzhiyun					0x1fc MODE_NITRO /* spi1_sck */
296*4882a593Smuzhiyun					0x200 MODE_NITRO /* spi1_rxd */
297*4882a593Smuzhiyun					0x204 MODE_NITRO /* spi1_fss */
298*4882a593Smuzhiyun					0x208 MODE_NITRO /* spi1_txd */
299*4882a593Smuzhiyun				>;
300*4882a593Smuzhiyun			};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun			nuart_pins: pinmux_uart0_sin_nitro {
303*4882a593Smuzhiyun				pinctrl-single,pins = <
304*4882a593Smuzhiyun					0x20c MODE_NITRO /* nuart_rxd */
305*4882a593Smuzhiyun					0x210 MODE_NITRO /* nuart_txd */
306*4882a593Smuzhiyun				>;
307*4882a593Smuzhiyun			};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun			uart0_pins: pinumux_uart0_sin_nand {
310*4882a593Smuzhiyun				pinctrl-single,pins = <
311*4882a593Smuzhiyun					0x20c MODE_NAND /* uart0_sin */
312*4882a593Smuzhiyun					0x210 MODE_NAND /* uart0_out */
313*4882a593Smuzhiyun					0x214 MODE_NAND /* uart0_rts */
314*4882a593Smuzhiyun					0x218 MODE_NAND /* uart0_cts */
315*4882a593Smuzhiyun					0x21c MODE_NAND /* uart0_dtr */
316*4882a593Smuzhiyun					0x220 MODE_NAND /* uart0_dcd */
317*4882a593Smuzhiyun					0x224 MODE_NAND /* uart0_dsr */
318*4882a593Smuzhiyun					0x228 MODE_NAND /* uart0_ri */
319*4882a593Smuzhiyun				>;
320*4882a593Smuzhiyun			};
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun			drdu2_pins: pinmux_drdu2_overcurrent {
323*4882a593Smuzhiyun				pinctrl-single,pins = <
324*4882a593Smuzhiyun					0x22c MODE_NITRO /* drdu2_overcurrent */
325*4882a593Smuzhiyun					0x230 MODE_NITRO /* drdu2_vbus_ppc */
326*4882a593Smuzhiyun					0x234 MODE_NITRO /* drdu2_vbus_present */
327*4882a593Smuzhiyun					0x238 MODE_NITRO /* drdu2_id */
328*4882a593Smuzhiyun				>;
329*4882a593Smuzhiyun			};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun			drdu3_pins: pinmux_drdu3_overcurrent {
332*4882a593Smuzhiyun				pinctrl-single,pins = <
333*4882a593Smuzhiyun					0x23c MODE_NITRO /* drdu3_overcurrent */
334*4882a593Smuzhiyun					0x240 MODE_NITRO /* drdu3_vbus_ppc */
335*4882a593Smuzhiyun					0x244 MODE_NITRO /* drdu3_vbus_present */
336*4882a593Smuzhiyun					0x248 MODE_NITRO /* drdu3_id */
337*4882a593Smuzhiyun				>;
338*4882a593Smuzhiyun			};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun			usb3h_pins: pinmux_usb3h_overcurrent {
341*4882a593Smuzhiyun				pinctrl-single,pins = <
342*4882a593Smuzhiyun					0x24c MODE_NITRO /* usb3h_overcurrent */
343*4882a593Smuzhiyun					0x250 MODE_NITRO /* usb3h_vbus_ppc */
344*4882a593Smuzhiyun				>;
345*4882a593Smuzhiyun			};
346*4882a593Smuzhiyun		};
347