1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * ARM Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * ARMv8 Foundation model DTS (spin table configuration) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun&cpu0 { 8*4882a593Smuzhiyun enable-method = "spin-table"; 9*4882a593Smuzhiyun cpu-release-addr = <0x0 0x8000fff8>; 10*4882a593Smuzhiyun}; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun&cpu1 { 13*4882a593Smuzhiyun enable-method = "spin-table"; 14*4882a593Smuzhiyun cpu-release-addr = <0x0 0x8000fff8>; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&cpu2 { 18*4882a593Smuzhiyun enable-method = "spin-table"; 19*4882a593Smuzhiyun cpu-release-addr = <0x0 0x8000fff8>; 20*4882a593Smuzhiyun}; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun&cpu3 { 23*4882a593Smuzhiyun enable-method = "spin-table"; 24*4882a593Smuzhiyun cpu-release-addr = <0x0 0x8000fff8>; 25*4882a593Smuzhiyun}; 26