1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * ARM Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * ARMv8 Foundation model DTS (GICv3 configuration) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun gic: interrupt-controller@2f000000 { 9*4882a593Smuzhiyun compatible = "arm,gic-v3"; 10*4882a593Smuzhiyun #interrupt-cells = <3>; 11*4882a593Smuzhiyun #address-cells = <1>; 12*4882a593Smuzhiyun #size-cells = <1>; 13*4882a593Smuzhiyun ranges = <0x0 0x0 0x2f000000 0x100000>; 14*4882a593Smuzhiyun interrupt-controller; 15*4882a593Smuzhiyun reg = <0x0 0x2f000000 0x0 0x10000>, 16*4882a593Smuzhiyun <0x0 0x2f100000 0x0 0x200000>, 17*4882a593Smuzhiyun <0x0 0x2c000000 0x0 0x2000>, 18*4882a593Smuzhiyun <0x0 0x2c010000 0x0 0x2000>, 19*4882a593Smuzhiyun <0x0 0x2c02f000 0x0 0x2000>; 20*4882a593Smuzhiyun interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun its: msi-controller@2f020000 { 23*4882a593Smuzhiyun compatible = "arm,gic-v3-its"; 24*4882a593Smuzhiyun msi-controller; 25*4882a593Smuzhiyun #msi-cells = <1>; 26*4882a593Smuzhiyun reg = <0x20000 0x20000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30