1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * ARM Ltd. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * ARMv8 Foundation model DTS (GICv2 configuration) 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun gic: interrupt-controller@2c001000 { 9*4882a593Smuzhiyun compatible = "arm,gic-400", "arm,cortex-a15-gic"; 10*4882a593Smuzhiyun #interrupt-cells = <3>; 11*4882a593Smuzhiyun #address-cells = <1>; 12*4882a593Smuzhiyun interrupt-controller; 13*4882a593Smuzhiyun reg = <0x0 0x2c001000 0 0x1000>, 14*4882a593Smuzhiyun <0x0 0x2c002000 0 0x2000>, 15*4882a593Smuzhiyun <0x0 0x2c004000 0 0x2000>, 16*4882a593Smuzhiyun <0x0 0x2c006000 0 0x2000>; 17*4882a593Smuzhiyun interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun}; 20