1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 BayLibre, SAS 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "meson-sm1.dtsi" 10*4882a593Smuzhiyun#include "meson-khadas-vim3.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/sound/meson-g12a-tohdmitx.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun compatible = "khadas,vim3l", "amlogic,sm1"; 15*4882a593Smuzhiyun model = "Khadas VIM3L"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun vddcpu: regulator-vddcpu { 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * Silergy SY8030DEC Regulator. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun compatible = "pwm-regulator"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun regulator-name = "VDDCPU"; 24*4882a593Smuzhiyun regulator-min-microvolt = <690000>; 25*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun vin-supply = <&vsys_3v3>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun pwms = <&pwm_AO_cd 1 1250 0>; 30*4882a593Smuzhiyun pwm-dutycycle-range = <100 0>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun regulator-boot-on; 33*4882a593Smuzhiyun regulator-always-on; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&cpu0 { 38*4882a593Smuzhiyun cpu-supply = <&vddcpu>; 39*4882a593Smuzhiyun operating-points-v2 = <&cpu_opp_table>; 40*4882a593Smuzhiyun clocks = <&clkc CLKID_CPU_CLK>; 41*4882a593Smuzhiyun clock-latency = <50000>; 42*4882a593Smuzhiyun}; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&cpu1 { 45*4882a593Smuzhiyun cpu-supply = <&vddcpu>; 46*4882a593Smuzhiyun operating-points-v2 = <&cpu_opp_table>; 47*4882a593Smuzhiyun clocks = <&clkc CLKID_CPU1_CLK>; 48*4882a593Smuzhiyun clock-latency = <50000>; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&cpu2 { 52*4882a593Smuzhiyun cpu-supply = <&vddcpu>; 53*4882a593Smuzhiyun operating-points-v2 = <&cpu_opp_table>; 54*4882a593Smuzhiyun clocks = <&clkc CLKID_CPU2_CLK>; 55*4882a593Smuzhiyun clock-latency = <50000>; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&cpu3 { 59*4882a593Smuzhiyun cpu-supply = <&vddcpu>; 60*4882a593Smuzhiyun operating-points-v2 = <&cpu_opp_table>; 61*4882a593Smuzhiyun clocks = <&clkc CLKID_CPU3_CLK>; 62*4882a593Smuzhiyun clock-latency = <50000>; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&pwm_AO_cd { 66*4882a593Smuzhiyun pinctrl-0 = <&pwm_ao_d_e_pins>; 67*4882a593Smuzhiyun pinctrl-names = "default"; 68*4882a593Smuzhiyun clocks = <&xtal>; 69*4882a593Smuzhiyun clock-names = "clkin1"; 70*4882a593Smuzhiyun status = "okay"; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun/* 74*4882a593Smuzhiyun * The VIM3 on-board MCU can mux the PCIe/USB3.0 shared differential 75*4882a593Smuzhiyun * lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between 76*4882a593Smuzhiyun * an USB3.0 Type A connector and a M.2 Key M slot. 77*4882a593Smuzhiyun * The PHY driving these differential lines is shared between 78*4882a593Smuzhiyun * the USB3.0 controller and the PCIe Controller, thus only 79*4882a593Smuzhiyun * a single controller can use it. 80*4882a593Smuzhiyun * If the MCU is configured to mux the PCIe/USB3.0 differential lines 81*4882a593Smuzhiyun * to the M.2 Key M slot, uncomment the following block to disable 82*4882a593Smuzhiyun * USB3.0 from the USB Complex and enable the PCIe controller. 83*4882a593Smuzhiyun * The End User is not expected to uncomment the following except for 84*4882a593Smuzhiyun * testing purposes, but instead rely on the firmware/bootloader to 85*4882a593Smuzhiyun * update these nodes accordingly if PCIe mode is selected by the MCU. 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun/* 88*4882a593Smuzhiyun&pcie { 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&usb { 93*4882a593Smuzhiyun phys = <&usb2_phy0>, <&usb2_phy1>; 94*4882a593Smuzhiyun phy-names = "usb2-phy0", "usb2-phy1"; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun */ 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&sd_emmc_a { 99*4882a593Smuzhiyun sd-uhs-sdr50; 100*4882a593Smuzhiyun}; 101