1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 BayLibre SAS. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun/plugin/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/phy/phy.h> 10*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 11*4882a593Smuzhiyun#include <dt-bindings/gpio/meson-g12a-gpio.h> 12*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 13*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun compatible = "khadas,vim3l", "amlogic,sm1"; 17*4882a593Smuzhiyun model = "Khadas VIM3L"; 18*4882a593Smuzhiyun fragment@101 { 19*4882a593Smuzhiyun target-path = "/"; 20*4882a593Smuzhiyun __overlay__ { 21*4882a593Smuzhiyun reserved-memory { 22*4882a593Smuzhiyun #address-cells = <2>; 23*4882a593Smuzhiyun #size-cells = <2>; 24*4882a593Smuzhiyun ramoops@d000000 { 25*4882a593Smuzhiyun compatible = "ramoops"; 26*4882a593Smuzhiyun reg = <0x0 0x0d000000 0x0 0x00100000>; 27*4882a593Smuzhiyun record-size = <0x8000>; 28*4882a593Smuzhiyun console-size = <0x8000>; 29*4882a593Smuzhiyun ftrace-size = <0x0>; 30*4882a593Smuzhiyun pmsg-size = <0x8000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&vcc_5v { 38*4882a593Smuzhiyun gpio-open-drain; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&uart_A { 42*4882a593Smuzhiyun bluetooth { 43*4882a593Smuzhiyun interrupt-parent = <&gpio_intc>; 44*4882a593Smuzhiyun interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; 45*4882a593Smuzhiyun interrupt-names = "host-wakeup"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&uart_C { 50*4882a593Smuzhiyun status = "disabled"; 51*4882a593Smuzhiyun pinctrl-0 = <&uart_c_pins>; 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&emmc_pwrseq{ 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun&sd_emmc_a { 60*4882a593Smuzhiyun /* WiFi firmware requires power to be kept while in suspend */ 61*4882a593Smuzhiyun keep-power-in-suspend; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun&spicc1 { 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun pinctrl-names = "default"; 67*4882a593Smuzhiyun pinctrl-0 = <&spicc1_pins>; 68*4882a593Smuzhiyun cs-gpios = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; 69*4882a593Smuzhiyun #address-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <0>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun spidev@0 { 73*4882a593Smuzhiyun compatible = "rohm,dh2228fv"; 74*4882a593Smuzhiyun reg = <0>; 75*4882a593Smuzhiyun spi-max-frequency = <500000>; 76*4882a593Smuzhiyun status = "okay"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun neonkey@0 { 80*4882a593Smuzhiyun compatible = "nanohub"; 81*4882a593Smuzhiyun reg = <0>; 82*4882a593Smuzhiyun spi-max-frequency = <500000>; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun sensorhub,nreset-gpio = <&gpio GPIOA_0 0>; 85*4882a593Smuzhiyun sensorhub,boot0-gpio = <&gpio GPIOA_3 0>; /* Fake */ 86*4882a593Smuzhiyun sensorhub,wakeup-gpio = <&gpio GPIOA_2 0>; /* A2 -> PB9 */ 87*4882a593Smuzhiyun sensorhub,irq1-gpio = <&gpio GPIOA_1 0>; /* A1 -> PB5 */ 88*4882a593Smuzhiyun interrupt-parent = <&gpio_intc>; 89*4882a593Smuzhiyun interrupts = <62 IRQ_TYPE_EDGE_RISING>; /* A1 */ 90*4882a593Smuzhiyun /* sensorhub,spi-cs-gpio = <&gpio GPIOH_6 GPIO_ACTIVE_LOW>; Optional */ 91*4882a593Smuzhiyun sensorhub,bl-addr = <0x08000000>; 92*4882a593Smuzhiyun sensorhub,kernel-addr = <0x0800C000>; 93*4882a593Smuzhiyun sensorhub,shared-addr = <0x08040000>; 94*4882a593Smuzhiyun sensorhub,flash-banks = <0 0x08000000 0x04000>, 95*4882a593Smuzhiyun <3 0x0800C000 0x04000>, 96*4882a593Smuzhiyun <4 0x08010000 0x10000>, 97*4882a593Smuzhiyun <5 0x08020000 0x20000>, 98*4882a593Smuzhiyun <6 0x08040000 0x20000>, 99*4882a593Smuzhiyun <7 0x08060000 0x20000>; 100*4882a593Smuzhiyun sensorhub,num-flash-banks = <6>; 101*4882a593Smuzhiyun status = "disabled"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun argonkey@0 { 105*4882a593Smuzhiyun compatible = "nanohub"; 106*4882a593Smuzhiyun reg = <0>; 107*4882a593Smuzhiyun spi-max-frequency = <500000>; 108*4882a593Smuzhiyun spi-cpol; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun sensorhub,nreset-gpio = <&gpio GPIOA_0 0>; 111*4882a593Smuzhiyun sensorhub,boot0-gpio = <&gpio GPIOA_3 0>; 112*4882a593Smuzhiyun sensorhub,wakeup-gpio = <&gpio GPIOA_1 0>; /* A1 -> PA0 */ 113*4882a593Smuzhiyun sensorhub,irq1-gpio = <&gpio GPIOA_2 0>; /* A2 -> PA1 */ 114*4882a593Smuzhiyun interrupt-parent = <&gpio_intc>; 115*4882a593Smuzhiyun interrupts = <63 IRQ_TYPE_EDGE_RISING>; /* A2 */ 116*4882a593Smuzhiyun sensorhub,bl-addr = <0x08000000>; 117*4882a593Smuzhiyun sensorhub,kernel-addr = <0x0800C000>; 118*4882a593Smuzhiyun sensorhub,num-flash-banks = <4>; 119*4882a593Smuzhiyun sensorhub,flash-banks = <0 0x08000000 0x04000>, 120*4882a593Smuzhiyun <3 0x0800C000 0x04000>, 121*4882a593Smuzhiyun <4 0x08010000 0x10000>, 122*4882a593Smuzhiyun <5 0x08020000 0x20000>; 123*4882a593Smuzhiyun sensorhub,shared-addr = <0x08040000>; 124*4882a593Smuzhiyun sensorhub,num-shared-flash-banks = <6>; 125*4882a593Smuzhiyun sensorhub,shared-flash-banks = <6 0x08040000 0x20000>, 126*4882a593Smuzhiyun <7 0x08060000 0x20000>, 127*4882a593Smuzhiyun <8 0x08080000 0x20000>, 128*4882a593Smuzhiyun <9 0x080A0000 0x20000>, 129*4882a593Smuzhiyun <10 0x080C0000 0x20000>, 130*4882a593Smuzhiyun <11 0x080E0000 0x20000>; 131*4882a593Smuzhiyun status = "disabled"; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun}; 134