1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 BayLibre, SAS 4*4882a593Smuzhiyun * Author: Neil Armstrong <narmstrong@baylibre.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "meson-g12.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun compatible = "amlogic,g12b"; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun cpus { 13*4882a593Smuzhiyun #address-cells = <0x2>; 14*4882a593Smuzhiyun #size-cells = <0x0>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun cpu-map { 17*4882a593Smuzhiyun cluster0 { 18*4882a593Smuzhiyun core0 { 19*4882a593Smuzhiyun cpu = <&cpu0>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun core1 { 23*4882a593Smuzhiyun cpu = <&cpu1>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun cluster1 { 28*4882a593Smuzhiyun core0 { 29*4882a593Smuzhiyun cpu = <&cpu100>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun core1 { 33*4882a593Smuzhiyun cpu = <&cpu101>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun core2 { 37*4882a593Smuzhiyun cpu = <&cpu102>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun core3 { 41*4882a593Smuzhiyun cpu = <&cpu103>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun cpu0: cpu@0 { 47*4882a593Smuzhiyun device_type = "cpu"; 48*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 49*4882a593Smuzhiyun reg = <0x0 0x0>; 50*4882a593Smuzhiyun enable-method = "psci"; 51*4882a593Smuzhiyun capacity-dmips-mhz = <592>; 52*4882a593Smuzhiyun next-level-cache = <&l2>; 53*4882a593Smuzhiyun #cooling-cells = <2>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun cpu1: cpu@1 { 57*4882a593Smuzhiyun device_type = "cpu"; 58*4882a593Smuzhiyun compatible = "arm,cortex-a53"; 59*4882a593Smuzhiyun reg = <0x0 0x1>; 60*4882a593Smuzhiyun enable-method = "psci"; 61*4882a593Smuzhiyun capacity-dmips-mhz = <592>; 62*4882a593Smuzhiyun next-level-cache = <&l2>; 63*4882a593Smuzhiyun #cooling-cells = <2>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun cpu100: cpu@100 { 67*4882a593Smuzhiyun device_type = "cpu"; 68*4882a593Smuzhiyun compatible = "arm,cortex-a73"; 69*4882a593Smuzhiyun reg = <0x0 0x100>; 70*4882a593Smuzhiyun enable-method = "psci"; 71*4882a593Smuzhiyun capacity-dmips-mhz = <1024>; 72*4882a593Smuzhiyun next-level-cache = <&l2>; 73*4882a593Smuzhiyun #cooling-cells = <2>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun cpu101: cpu@101 { 77*4882a593Smuzhiyun device_type = "cpu"; 78*4882a593Smuzhiyun compatible = "arm,cortex-a73"; 79*4882a593Smuzhiyun reg = <0x0 0x101>; 80*4882a593Smuzhiyun enable-method = "psci"; 81*4882a593Smuzhiyun capacity-dmips-mhz = <1024>; 82*4882a593Smuzhiyun next-level-cache = <&l2>; 83*4882a593Smuzhiyun #cooling-cells = <2>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun cpu102: cpu@102 { 87*4882a593Smuzhiyun device_type = "cpu"; 88*4882a593Smuzhiyun compatible = "arm,cortex-a73"; 89*4882a593Smuzhiyun reg = <0x0 0x102>; 90*4882a593Smuzhiyun enable-method = "psci"; 91*4882a593Smuzhiyun capacity-dmips-mhz = <1024>; 92*4882a593Smuzhiyun next-level-cache = <&l2>; 93*4882a593Smuzhiyun #cooling-cells = <2>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun cpu103: cpu@103 { 97*4882a593Smuzhiyun device_type = "cpu"; 98*4882a593Smuzhiyun compatible = "arm,cortex-a73"; 99*4882a593Smuzhiyun reg = <0x0 0x103>; 100*4882a593Smuzhiyun enable-method = "psci"; 101*4882a593Smuzhiyun capacity-dmips-mhz = <1024>; 102*4882a593Smuzhiyun next-level-cache = <&l2>; 103*4882a593Smuzhiyun #cooling-cells = <2>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun l2: l2-cache0 { 107*4882a593Smuzhiyun compatible = "cache"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&clkc { 113*4882a593Smuzhiyun compatible = "amlogic,g12b-clkc"; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&cpu_thermal { 117*4882a593Smuzhiyun cooling-maps { 118*4882a593Smuzhiyun map0 { 119*4882a593Smuzhiyun trip = <&cpu_passive>; 120*4882a593Smuzhiyun cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 121*4882a593Smuzhiyun <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 122*4882a593Smuzhiyun <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 123*4882a593Smuzhiyun <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 124*4882a593Smuzhiyun <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 125*4882a593Smuzhiyun <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun map1 { 128*4882a593Smuzhiyun trip = <&cpu_hot>; 129*4882a593Smuzhiyun cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 130*4882a593Smuzhiyun <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 131*4882a593Smuzhiyun <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 132*4882a593Smuzhiyun <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 133*4882a593Smuzhiyun <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 134*4882a593Smuzhiyun <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun}; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun&mali { 140*4882a593Smuzhiyun dma-coherent; 141*4882a593Smuzhiyun}; 142