1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for AMD Seattle XGBE (RevB) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Advanced Micro Devices, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun xgmacclk0_dma_250mhz: clk250mhz_0 { 9*4882a593Smuzhiyun compatible = "fixed-clock"; 10*4882a593Smuzhiyun #clock-cells = <0>; 11*4882a593Smuzhiyun clock-frequency = <250000000>; 12*4882a593Smuzhiyun clock-output-names = "xgmacclk0_dma_250mhz"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun xgmacclk0_ptp_250mhz: clk250mhz_1 { 16*4882a593Smuzhiyun compatible = "fixed-clock"; 17*4882a593Smuzhiyun #clock-cells = <0>; 18*4882a593Smuzhiyun clock-frequency = <250000000>; 19*4882a593Smuzhiyun clock-output-names = "xgmacclk0_ptp_250mhz"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun xgmacclk1_dma_250mhz: clk250mhz_2 { 23*4882a593Smuzhiyun compatible = "fixed-clock"; 24*4882a593Smuzhiyun #clock-cells = <0>; 25*4882a593Smuzhiyun clock-frequency = <250000000>; 26*4882a593Smuzhiyun clock-output-names = "xgmacclk1_dma_250mhz"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun xgmacclk1_ptp_250mhz: clk250mhz_3 { 30*4882a593Smuzhiyun compatible = "fixed-clock"; 31*4882a593Smuzhiyun #clock-cells = <0>; 32*4882a593Smuzhiyun clock-frequency = <250000000>; 33*4882a593Smuzhiyun clock-output-names = "xgmacclk1_ptp_250mhz"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun xgmac0: xgmac@e0700000 { 37*4882a593Smuzhiyun compatible = "amd,xgbe-seattle-v1a"; 38*4882a593Smuzhiyun reg = <0 0xe0700000 0 0x80000>, 39*4882a593Smuzhiyun <0 0xe0780000 0 0x80000>, 40*4882a593Smuzhiyun <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */ 41*4882a593Smuzhiyun <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */ 42*4882a593Smuzhiyun <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */ 43*4882a593Smuzhiyun interrupts = <0 325 4>, 44*4882a593Smuzhiyun <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>, 45*4882a593Smuzhiyun <0 323 4>; 46*4882a593Smuzhiyun amd,per-channel-interrupt; 47*4882a593Smuzhiyun amd,speed-set = <0>; 48*4882a593Smuzhiyun amd,serdes-blwc = <1>, <1>, <0>; 49*4882a593Smuzhiyun amd,serdes-cdr-rate = <2>, <2>, <7>; 50*4882a593Smuzhiyun amd,serdes-pq-skew = <10>, <10>, <18>; 51*4882a593Smuzhiyun amd,serdes-tx-amp = <0>, <0>, <0>; 52*4882a593Smuzhiyun amd,serdes-dfe-tap-config = <3>, <3>, <3>; 53*4882a593Smuzhiyun amd,serdes-dfe-tap-enable = <0>, <0>, <7>; 54*4882a593Smuzhiyun mac-address = [ 02 A1 A2 A3 A4 A5 ]; 55*4882a593Smuzhiyun clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>; 56*4882a593Smuzhiyun clock-names = "dma_clk", "ptp_clk"; 57*4882a593Smuzhiyun phy-mode = "xgmii"; 58*4882a593Smuzhiyun #stream-id-cells = <16>; 59*4882a593Smuzhiyun dma-coherent; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun xgmac1: xgmac@e0900000 { 63*4882a593Smuzhiyun compatible = "amd,xgbe-seattle-v1a"; 64*4882a593Smuzhiyun reg = <0 0xe0900000 0 0x80000>, 65*4882a593Smuzhiyun <0 0xe0980000 0 0x80000>, 66*4882a593Smuzhiyun <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */ 67*4882a593Smuzhiyun <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */ 68*4882a593Smuzhiyun <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */ 69*4882a593Smuzhiyun interrupts = <0 324 4>, 70*4882a593Smuzhiyun <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>, 71*4882a593Smuzhiyun <0 322 4>; 72*4882a593Smuzhiyun amd,per-channel-interrupt; 73*4882a593Smuzhiyun amd,speed-set = <0>; 74*4882a593Smuzhiyun amd,serdes-blwc = <1>, <1>, <0>; 75*4882a593Smuzhiyun amd,serdes-cdr-rate = <2>, <2>, <7>; 76*4882a593Smuzhiyun amd,serdes-pq-skew = <10>, <10>, <18>; 77*4882a593Smuzhiyun amd,serdes-tx-amp = <0>, <0>, <0>; 78*4882a593Smuzhiyun amd,serdes-dfe-tap-config = <3>, <3>, <3>; 79*4882a593Smuzhiyun amd,serdes-dfe-tap-enable = <0>, <0>, <7>; 80*4882a593Smuzhiyun mac-address = [ 02 B1 B2 B3 B4 B5 ]; 81*4882a593Smuzhiyun clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>; 82*4882a593Smuzhiyun clock-names = "dma_clk", "ptp_clk"; 83*4882a593Smuzhiyun phy-mode = "xgmii"; 84*4882a593Smuzhiyun #stream-id-cells = <16>; 85*4882a593Smuzhiyun dma-coherent; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun xgmac0_smmu: smmu@e0600000 { 89*4882a593Smuzhiyun compatible = "arm,mmu-401"; 90*4882a593Smuzhiyun reg = <0 0xe0600000 0 0x10000>; 91*4882a593Smuzhiyun #global-interrupts = <1>; 92*4882a593Smuzhiyun interrupts = /* Uses combined intr for both 93*4882a593Smuzhiyun * global and context 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun <0 336 4>, 96*4882a593Smuzhiyun <0 336 4>; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun mmu-masters = <&xgmac0 99*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 100*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 101*4882a593Smuzhiyun >; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun xgmac1_smmu: smmu@e0800000 { 105*4882a593Smuzhiyun compatible = "arm,mmu-401"; 106*4882a593Smuzhiyun reg = <0 0xe0800000 0 0x10000>; 107*4882a593Smuzhiyun #global-interrupts = <1>; 108*4882a593Smuzhiyun interrupts = /* Uses combined intr for both 109*4882a593Smuzhiyun * global and context 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun <0 335 4>, 112*4882a593Smuzhiyun <0 335 4>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun mmu-masters = <&xgmac1 115*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 116*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 117*4882a593Smuzhiyun >; 118*4882a593Smuzhiyun }; 119