1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for AMD Seattle SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Advanced Micro Devices, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun compatible = "amd,seattle"; 10*4882a593Smuzhiyun interrupt-parent = <&gic0>; 11*4882a593Smuzhiyun #address-cells = <2>; 12*4882a593Smuzhiyun #size-cells = <2>; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun gic0: interrupt-controller@e1101000 { 15*4882a593Smuzhiyun compatible = "arm,gic-400", "arm,cortex-a15-gic"; 16*4882a593Smuzhiyun interrupt-controller; 17*4882a593Smuzhiyun #interrupt-cells = <3>; 18*4882a593Smuzhiyun #address-cells = <2>; 19*4882a593Smuzhiyun #size-cells = <2>; 20*4882a593Smuzhiyun reg = <0x0 0xe1110000 0 0x1000>, 21*4882a593Smuzhiyun <0x0 0xe112f000 0 0x2000>, 22*4882a593Smuzhiyun <0x0 0xe1140000 0 0x2000>, 23*4882a593Smuzhiyun <0x0 0xe1160000 0 0x2000>; 24*4882a593Smuzhiyun interrupts = <1 9 0xf04>; 25*4882a593Smuzhiyun ranges = <0 0 0 0xe1100000 0 0x100000>; 26*4882a593Smuzhiyun v2m0: v2m@e0080000 { 27*4882a593Smuzhiyun compatible = "arm,gic-v2m-frame"; 28*4882a593Smuzhiyun msi-controller; 29*4882a593Smuzhiyun reg = <0x0 0x00080000 0 0x1000>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun timer { 34*4882a593Smuzhiyun compatible = "arm,armv8-timer"; 35*4882a593Smuzhiyun interrupts = <1 13 0xff04>, 36*4882a593Smuzhiyun <1 14 0xff04>, 37*4882a593Smuzhiyun <1 11 0xff04>, 38*4882a593Smuzhiyun <1 10 0xff04>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun pmu { 42*4882a593Smuzhiyun compatible = "arm,armv8-pmuv3"; 43*4882a593Smuzhiyun interrupts = <0 7 4>, 44*4882a593Smuzhiyun <0 8 4>, 45*4882a593Smuzhiyun <0 9 4>, 46*4882a593Smuzhiyun <0 10 4>, 47*4882a593Smuzhiyun <0 11 4>, 48*4882a593Smuzhiyun <0 12 4>, 49*4882a593Smuzhiyun <0 13 4>, 50*4882a593Smuzhiyun <0 14 4>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun smb0: smb { 54*4882a593Smuzhiyun compatible = "simple-bus"; 55*4882a593Smuzhiyun #address-cells = <2>; 56*4882a593Smuzhiyun #size-cells = <2>; 57*4882a593Smuzhiyun ranges; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * dma-ranges is 40-bit address space containing: 61*4882a593Smuzhiyun * - GICv2m MSI register is at 0xe0080000 62*4882a593Smuzhiyun * - DRAM range [0x8000000000 to 0xffffffffff] 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /include/ "amd-seattle-clks.dtsi" 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun sata0: sata@e0300000 { 69*4882a593Smuzhiyun compatible = "snps,dwc-ahci"; 70*4882a593Smuzhiyun reg = <0 0xe0300000 0 0xf0000>; 71*4882a593Smuzhiyun interrupts = <0 355 4>; 72*4882a593Smuzhiyun clocks = <&sataclk_333mhz>; 73*4882a593Smuzhiyun dma-coherent; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* This is for Rev B only */ 77*4882a593Smuzhiyun sata1: sata@e0d00000 { 78*4882a593Smuzhiyun status = "disabled"; 79*4882a593Smuzhiyun compatible = "snps,dwc-ahci"; 80*4882a593Smuzhiyun reg = <0 0xe0d00000 0 0xf0000>; 81*4882a593Smuzhiyun interrupts = <0 354 4>; 82*4882a593Smuzhiyun clocks = <&sataclk_333mhz>; 83*4882a593Smuzhiyun dma-coherent; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun i2c0: i2c@e1000000 { 87*4882a593Smuzhiyun status = "disabled"; 88*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 89*4882a593Smuzhiyun reg = <0 0xe1000000 0 0x1000>; 90*4882a593Smuzhiyun interrupts = <0 357 4>; 91*4882a593Smuzhiyun clocks = <&miscclk_250mhz>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun i2c1: i2c@e0050000 { 95*4882a593Smuzhiyun status = "disabled"; 96*4882a593Smuzhiyun compatible = "snps,designware-i2c"; 97*4882a593Smuzhiyun reg = <0 0xe0050000 0 0x1000>; 98*4882a593Smuzhiyun interrupts = <0 340 4>; 99*4882a593Smuzhiyun clocks = <&miscclk_250mhz>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun serial0: serial@e1010000 { 103*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 104*4882a593Smuzhiyun reg = <0 0xe1010000 0 0x1000>; 105*4882a593Smuzhiyun interrupts = <0 328 4>; 106*4882a593Smuzhiyun clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; 107*4882a593Smuzhiyun clock-names = "uartclk", "apb_pclk"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun spi0: spi@e1020000 { 111*4882a593Smuzhiyun status = "disabled"; 112*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 113*4882a593Smuzhiyun reg = <0 0xe1020000 0 0x1000>; 114*4882a593Smuzhiyun spi-controller; 115*4882a593Smuzhiyun interrupts = <0 330 4>; 116*4882a593Smuzhiyun clocks = <&uartspiclk_100mhz>; 117*4882a593Smuzhiyun clock-names = "apb_pclk"; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun spi1: spi@e1030000 { 121*4882a593Smuzhiyun status = "disabled"; 122*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 123*4882a593Smuzhiyun reg = <0 0xe1030000 0 0x1000>; 124*4882a593Smuzhiyun spi-controller; 125*4882a593Smuzhiyun interrupts = <0 329 4>; 126*4882a593Smuzhiyun clocks = <&uartspiclk_100mhz>; 127*4882a593Smuzhiyun clock-names = "apb_pclk"; 128*4882a593Smuzhiyun num-cs = <1>; 129*4882a593Smuzhiyun #address-cells = <1>; 130*4882a593Smuzhiyun #size-cells = <0>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun gpio0: gpio@e1040000 { /* Not available to OS for B0 */ 134*4882a593Smuzhiyun status = "disabled"; 135*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 136*4882a593Smuzhiyun #gpio-cells = <2>; 137*4882a593Smuzhiyun reg = <0 0xe1040000 0 0x1000>; 138*4882a593Smuzhiyun gpio-controller; 139*4882a593Smuzhiyun interrupts = <0 359 4>; 140*4882a593Smuzhiyun interrupt-controller; 141*4882a593Smuzhiyun #interrupt-cells = <2>; 142*4882a593Smuzhiyun clocks = <&miscclk_250mhz>; 143*4882a593Smuzhiyun clock-names = "apb_pclk"; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun gpio1: gpio@e1050000 { /* [0:7] */ 147*4882a593Smuzhiyun status = "disabled"; 148*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 149*4882a593Smuzhiyun #gpio-cells = <2>; 150*4882a593Smuzhiyun reg = <0 0xe1050000 0 0x1000>; 151*4882a593Smuzhiyun gpio-controller; 152*4882a593Smuzhiyun interrupt-controller; 153*4882a593Smuzhiyun #interrupt-cells = <2>; 154*4882a593Smuzhiyun interrupts = <0 358 4>; 155*4882a593Smuzhiyun clocks = <&miscclk_250mhz>; 156*4882a593Smuzhiyun clock-names = "apb_pclk"; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun gpio2: gpio@e0020000 { /* [8:15] */ 160*4882a593Smuzhiyun status = "disabled"; 161*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 162*4882a593Smuzhiyun #gpio-cells = <2>; 163*4882a593Smuzhiyun reg = <0 0xe0020000 0 0x1000>; 164*4882a593Smuzhiyun gpio-controller; 165*4882a593Smuzhiyun interrupt-controller; 166*4882a593Smuzhiyun #interrupt-cells = <2>; 167*4882a593Smuzhiyun interrupts = <0 366 4>; 168*4882a593Smuzhiyun clocks = <&miscclk_250mhz>; 169*4882a593Smuzhiyun clock-names = "apb_pclk"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun gpio3: gpio@e0030000 { /* [16:23] */ 173*4882a593Smuzhiyun status = "disabled"; 174*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 175*4882a593Smuzhiyun #gpio-cells = <2>; 176*4882a593Smuzhiyun reg = <0 0xe0030000 0 0x1000>; 177*4882a593Smuzhiyun gpio-controller; 178*4882a593Smuzhiyun interrupt-controller; 179*4882a593Smuzhiyun #interrupt-cells = <2>; 180*4882a593Smuzhiyun interrupts = <0 365 4>; 181*4882a593Smuzhiyun clocks = <&miscclk_250mhz>; 182*4882a593Smuzhiyun clock-names = "apb_pclk"; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun gpio4: gpio@e0080000 { /* [24] */ 186*4882a593Smuzhiyun status = "disabled"; 187*4882a593Smuzhiyun compatible = "arm,pl061", "arm,primecell"; 188*4882a593Smuzhiyun #gpio-cells = <2>; 189*4882a593Smuzhiyun reg = <0 0xe0080000 0 0x1000>; 190*4882a593Smuzhiyun gpio-controller; 191*4882a593Smuzhiyun interrupt-controller; 192*4882a593Smuzhiyun #interrupt-cells = <2>; 193*4882a593Smuzhiyun interrupts = <0 361 4>; 194*4882a593Smuzhiyun clocks = <&miscclk_250mhz>; 195*4882a593Smuzhiyun clock-names = "apb_pclk"; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun ccp0: ccp@e0100000 { 199*4882a593Smuzhiyun status = "disabled"; 200*4882a593Smuzhiyun compatible = "amd,ccp-seattle-v1a"; 201*4882a593Smuzhiyun reg = <0 0xe0100000 0 0x10000>; 202*4882a593Smuzhiyun interrupts = <0 3 4>; 203*4882a593Smuzhiyun dma-coherent; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun pcie0: pcie@f0000000 { 207*4882a593Smuzhiyun compatible = "pci-host-ecam-generic"; 208*4882a593Smuzhiyun #address-cells = <3>; 209*4882a593Smuzhiyun #size-cells = <2>; 210*4882a593Smuzhiyun #interrupt-cells = <1>; 211*4882a593Smuzhiyun device_type = "pci"; 212*4882a593Smuzhiyun bus-range = <0 0x7f>; 213*4882a593Smuzhiyun msi-parent = <&v2m0>; 214*4882a593Smuzhiyun reg = <0 0xf0000000 0 0x10000000>; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 217*4882a593Smuzhiyun interrupt-map = 218*4882a593Smuzhiyun <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>, 219*4882a593Smuzhiyun <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>, 220*4882a593Smuzhiyun <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>, 221*4882a593Smuzhiyun <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun dma-coherent; 224*4882a593Smuzhiyun dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>; 225*4882a593Smuzhiyun ranges = 226*4882a593Smuzhiyun /* I/O Memory (size=64K) */ 227*4882a593Smuzhiyun <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>, 228*4882a593Smuzhiyun /* 32-bit MMIO (size=2G) */ 229*4882a593Smuzhiyun <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>, 230*4882a593Smuzhiyun /* 64-bit MMIO (size= 124G) */ 231*4882a593Smuzhiyun <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* Perf CCN504 PMU */ 235*4882a593Smuzhiyun ccn: ccn@e8000000 { 236*4882a593Smuzhiyun compatible = "arm,ccn-504"; 237*4882a593Smuzhiyun reg = <0x0 0xe8000000 0 0x1000000>; 238*4882a593Smuzhiyun interrupts = <0 380 4>; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun ipmi_kcs: kcs@e0010000 { 242*4882a593Smuzhiyun status = "disabled"; 243*4882a593Smuzhiyun compatible = "ipmi-kcs"; 244*4882a593Smuzhiyun device_type = "ipmi"; 245*4882a593Smuzhiyun reg = <0x0 0xe0010000 0 0x8>; 246*4882a593Smuzhiyun interrupts = <0 389 4>; 247*4882a593Smuzhiyun reg-size = <1>; 248*4882a593Smuzhiyun reg-spacing = <4>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun}; 252