1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for AMD Seattle Clocks 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Advanced Micro Devices, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun adl3clk_100mhz: clk100mhz_0 { 9*4882a593Smuzhiyun compatible = "fixed-clock"; 10*4882a593Smuzhiyun #clock-cells = <0>; 11*4882a593Smuzhiyun clock-frequency = <100000000>; 12*4882a593Smuzhiyun clock-output-names = "adl3clk_100mhz"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun ccpclk_375mhz: clk375mhz { 16*4882a593Smuzhiyun compatible = "fixed-clock"; 17*4882a593Smuzhiyun #clock-cells = <0>; 18*4882a593Smuzhiyun clock-frequency = <375000000>; 19*4882a593Smuzhiyun clock-output-names = "ccpclk_375mhz"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun sataclk_333mhz: clk333mhz { 23*4882a593Smuzhiyun compatible = "fixed-clock"; 24*4882a593Smuzhiyun #clock-cells = <0>; 25*4882a593Smuzhiyun clock-frequency = <333000000>; 26*4882a593Smuzhiyun clock-output-names = "sataclk_333mhz"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun pcieclk_500mhz: clk500mhz_0 { 30*4882a593Smuzhiyun compatible = "fixed-clock"; 31*4882a593Smuzhiyun #clock-cells = <0>; 32*4882a593Smuzhiyun clock-frequency = <500000000>; 33*4882a593Smuzhiyun clock-output-names = "pcieclk_500mhz"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun dmaclk_500mhz: clk500mhz_1 { 37*4882a593Smuzhiyun compatible = "fixed-clock"; 38*4882a593Smuzhiyun #clock-cells = <0>; 39*4882a593Smuzhiyun clock-frequency = <500000000>; 40*4882a593Smuzhiyun clock-output-names = "dmaclk_500mhz"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun miscclk_250mhz: clk250mhz_4 { 44*4882a593Smuzhiyun compatible = "fixed-clock"; 45*4882a593Smuzhiyun #clock-cells = <0>; 46*4882a593Smuzhiyun clock-frequency = <250000000>; 47*4882a593Smuzhiyun clock-output-names = "miscclk_250mhz"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun uartspiclk_100mhz: clk100mhz_1 { 51*4882a593Smuzhiyun compatible = "fixed-clock"; 52*4882a593Smuzhiyun #clock-cells = <0>; 53*4882a593Smuzhiyun clock-frequency = <100000000>; 54*4882a593Smuzhiyun clock-output-names = "uartspiclk_100mhz"; 55*4882a593Smuzhiyun }; 56