1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun// Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz> 3*4882a593Smuzhiyun// Based on sun50i-a64-pine64.dts, which is: 4*4882a593Smuzhiyun// Copyright (c) 2016 ARM Ltd. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "sun50i-a64.dtsi" 7*4882a593Smuzhiyun#include "sun50i-a64-cpu-opp.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun&codec_analog { 12*4882a593Smuzhiyun cpvdd-supply = <®_eldo1>; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun&cpu0 { 16*4882a593Smuzhiyun cpu-supply = <®_dcdc2>; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun&cpu1 { 20*4882a593Smuzhiyun cpu-supply = <®_dcdc2>; 21*4882a593Smuzhiyun}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun&cpu2 { 24*4882a593Smuzhiyun cpu-supply = <®_dcdc2>; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&cpu3 { 28*4882a593Smuzhiyun cpu-supply = <®_dcdc2>; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun&mmc0 { 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun pinctrl-0 = <&mmc0_pins>; 34*4882a593Smuzhiyun vmmc-supply = <®_dcdc1>; 35*4882a593Smuzhiyun disable-wp; 36*4882a593Smuzhiyun bus-width = <4>; 37*4882a593Smuzhiyun cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */ 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&r_rsb { 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun axp803: pmic@3a3 { 45*4882a593Smuzhiyun compatible = "x-powers,axp803"; 46*4882a593Smuzhiyun reg = <0x3a3>; 47*4882a593Smuzhiyun interrupt-parent = <&r_intc>; 48*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&spi0 { 53*4882a593Smuzhiyun status = "okay"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun flash@0 { 56*4882a593Smuzhiyun #address-cells = <1>; 57*4882a593Smuzhiyun #size-cells = <1>; 58*4882a593Smuzhiyun compatible = "jedec,spi-nor"; 59*4882a593Smuzhiyun reg = <0>; 60*4882a593Smuzhiyun spi-max-frequency = <40000000>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun}; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun#include "axp803.dtsi" 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun®_aldo2 { 67*4882a593Smuzhiyun regulator-always-on; 68*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 69*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 70*4882a593Smuzhiyun regulator-name = "vcc-pl"; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun®_aldo3 { 74*4882a593Smuzhiyun regulator-always-on; 75*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 76*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 77*4882a593Smuzhiyun regulator-name = "vcc-pll-avcc"; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun®_dcdc1 { 81*4882a593Smuzhiyun regulator-always-on; 82*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 83*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 84*4882a593Smuzhiyun regulator-name = "vcc-3v3"; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun®_dcdc2 { 88*4882a593Smuzhiyun regulator-always-on; 89*4882a593Smuzhiyun regulator-min-microvolt = <1040000>; 90*4882a593Smuzhiyun regulator-max-microvolt = <1300000>; 91*4882a593Smuzhiyun regulator-name = "vdd-cpux"; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun/* DCDC3 is polyphased with DCDC2 */ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun®_dcdc5 { 97*4882a593Smuzhiyun regulator-always-on; 98*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 99*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 100*4882a593Smuzhiyun regulator-name = "vcc-dram"; 101*4882a593Smuzhiyun}; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun®_dcdc6 { 104*4882a593Smuzhiyun regulator-always-on; 105*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 106*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 107*4882a593Smuzhiyun regulator-name = "vdd-sys"; 108*4882a593Smuzhiyun}; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun®_eldo1 { 111*4882a593Smuzhiyun regulator-always-on; 112*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 113*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 114*4882a593Smuzhiyun regulator-name = "vdd-1v8-lpddr"; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun®_fldo1 { 118*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 119*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 120*4882a593Smuzhiyun regulator-name = "vcc-1v2-hsic"; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun/* 124*4882a593Smuzhiyun * The A64 chip cannot work without this regulator off, although 125*4882a593Smuzhiyun * it seems to be only driving the AR100 core. 126*4882a593Smuzhiyun * Maybe we don't still know well about CPUs domain. 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun®_fldo2 { 129*4882a593Smuzhiyun regulator-always-on; 130*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 131*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 132*4882a593Smuzhiyun regulator-name = "vdd-cpus"; 133*4882a593Smuzhiyun}; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun®_rtc_ldo { 136*4882a593Smuzhiyun regulator-name = "vcc-rtc"; 137*4882a593Smuzhiyun}; 138